一個低功率的權重前饋控制串聯式積分器架構之二階三角積分器設計與實現

Abstract

隨著VLSI技術的演進，類比電路已經被實現在更低的提供電壓及更小的晶片面積。在各種低供電、低功率消耗的元件中，三角積分數位類比轉換器在音頻的可攜帶電子元件應用上的實現，是一種比起其他數位類比轉換器、在功率消耗上更有效率的一種實現方式。 本論文提出並經由台積電的0.18微米製程實現了一個低功率消耗的三角積分數位轉換器電路。經由將回路濾波器中的運算跨導放大器的規格做最佳化，一個電流最佳化的技術被提出。使用權重前饋控制串聯式積分器的調變器架構以及單級-A類加上正回授的運算跨導放大器電路，本論文提出的三角積分類比數位轉換調變器的訊號雜訊比到達63.4dB,並且能處理直流到最高16KHz的訊號。使用一伏特的供應電壓、整個調變器的功率消耗只有18微瓦特。

With the scaling down of VLSI technology, the analog circuit have implemented with a lower supply voltage and smaller chip area. Among the low-voltage low-power building blocks, the sigma-delta ADC provides a power-efficient way to implement an ADC for audio-band portable device applications. This thesis presents the design and implementation of a low power sigma-delta modulator (SDM) with a standard 0.18-□m CMOS technology. A current optimization technique is proposed by making a specification optimization of the Operational Transconductance Amplifier (OTA) in loop filter. Using a chain of Integrators with weighted feed-forward summation (CIFF) structure and a single-stage class-A OTA with positive feedback, the proposed second-order SDM achieves a SNR of 63.4dB that be able to process the signal form DC to 16KHz.The power consumption is only 18 uW from a 1-V supply.