H.264 CAVLC/CABAC熵解碼整合型IP設計

Abstract

在這論文中, 我們設計了一個H.264 CAVLC和CABAC熵解碼器的可合成電路, 我們利用Xilinx Vertex 5-based FPGA發展版, ML506, 和reference software JM 12.2來驗證我們的電路. 我們只利用了7000個slice (發展版的21%) 在50MHz下, 我們CAVLD和CABAD的效能可以達到11mbps和8mbps

In this thesis, we designed a synthesizable RTL model of the entropy decoder (CAVLC and CABAC) for the AVC (a.k.a. H.264) video coding standard. The design has been verified on the Xilinx Vertex 5-based FPGA development board, ML506, using full system verification with the AVC/H.264 reference software JM 12.2. The size of the combined CAVLD and CABAD logic is reasonably small. It only occupies about 7000 slices (21% logic resource of the target device). At a clock rate of 50MHz, the performance of the design can achieve decoding of bitrates over 11 mbps for CAVLD and 8 mbps for CABAC.