防護線對高速數位信號在板級的電磁干擾影響探討

Abstract

近年來科技進步，一日千里，產品為了可攜性，產品輕、薄、短小以及操作速度快發展。加上電子資訊產品已廣泛的受大眾使用，各地區對EMC問題也愈重視，因此『電磁相容』的問題在未來越來越重要。

本論文以在Ethernet Switch PCB 設計時常使用的二層板、操作頻率為125MHz，探討高速數位訊號快速切換時所造成的電磁干擾、電流迴流路徑及訊號完整性等問題，藉由使用Guard trace、終端技巧以及修補電流迴流路徑的方式，來抑制、減輕操作頻率上的雜訊。除此之外，本論文藉由簡單地計算輻射效率方式，對所導入的對策是否有效可得到一量化的比較值。

In recent years, the technology has made great progress. The design tendency towards light, flimsy, small technology products and therefore the portable and quick operation features of these technology products become very important. In addition, the electronic technology products are in widespread use by population. Many regions also take the EMC issue seriously. Therefore, the electromagnetic compatibility issue becomes more and more important in the future.

In this thesis, we design a two-layer PCB operating at a clock rate of 125MHz. The purpose of this thesis is to investigate the electromagnetic interference issue caused by the fast-changing of high-speed digital signal, return current path, and signal integrity. Using guard trace, the termination technology, and repairing return current path to suppress and mitigate the electromagnetic interference. Besides, this thesis calculates radiation efficiency to compare the effect of each inducted countermeasures for obtaining a qualified value.