結合鎳金屬吸附的製程技術搭配具有加厚之汲/源極與薄通道低溫複晶矽薄膜電晶體之研究

Abstract

在本研究中，第一部分是探討在鎳金屬誘發側向結晶的複晶矽薄膜中，矽化鎳會被針狀結晶間的晶界捕獲，造成金屬污染的問題。鎳金屬殘留在複晶矽主動層裡，造成薄膜電晶體特性及漏電流異常。因此，為了降低大量的矽化鎳殘留在複晶矽中，我們製作了結合鎳金屬吸附的製程技術搭配具有加厚之汲/源極與薄通道之低溫複晶矽薄膜電晶體，成功的將鎳金屬吸附出來，進而得到較高的載子遷移率和較低的次臨界擺幅與臨界電壓，也因具有加厚之汲/源極，使得汲極與通道接面處的電場下降，可得到較高的導通電流與抑制漏電流的能力。 第二部分是探討元件通道與鎳金屬誘發側向結晶在不同方向下，對下部閘極薄膜電晶體的元件特性影響。我們發現下部閘極薄膜電晶體的製作過程中，當鎳金屬誘發側向結晶時，會遇到下部閘極的阻礙，造成在通道與汲極的邊界產生很多的晶界與矽化鎳累積，晶界所產生的能障阻礙了載子的傳輸，使得載子遷移率下降，大量的矽化鎳累積使得汲極漏電流增加。

In this research, the first part is studying on metal induced lateral crystallization of amorphous silicon with Ni contamination issue. Ni trapped by grain boundary results in degradation of the device performance and increases of leakage current. In order to resolve the issue, we found out a method to fabricate of MILC Bottom Gate TFT with Ni-Gettering and raised Source/Drain structure. The Ni contamination was diminished after Ni-Gettering leads to get the higher carrier mobility and lower sub-threshold swing. By raised the Source/Drain structure, the electric field was suppressed. The leakage current can be reduced by decreasing the lateral electric field. The second part is studying the effect of MILC growth orientation on electrical properties of bottom gate MILC TFT. We observed lateral crystallization will meet the barrier by the bottom gate, Ni will trap at drain side leads to reduce the carrier mobility and increase the leakage current.