低介電常數材料應用於多層導體連線之電特性分析

Abstract

本論文研究積體電路製造技術中的低介電常數材料與多層銅導線連線整合製程之電特性分析及其相關技術之研究，並探討低介電常數材料應用於下一世代積體電路高頻訊號傳導的可能性。研究對象除了最成熟的Fluorosilicate Glass (FSG)外，還包括多孔隙型低介電常數材料如有機類的Nano-porous Carbon doped Oxide (CDO)以及旋轉塗佈型的Porous SiLK，以及低介電常數阻障層碳化矽(SiC)。 FSG是一含氟的氧化矽合物，主要以化學氣相沈積生成，是最接近傳統積體電路製程中二氧化矽的低介電膜，雖然介電係數約3.6，卻是目前唯一明確應用於積體電路量產的材料，因此利用FSG來討論其它各種低介電常數材料在整合製程時，因製程不同造成介電質表面損傷時，所需注意金屬離子擴散問題，並建立一簡單物理模型解釋此金屬離子擴散所造成介電質電特性不隱定現象。 極低介電常數材料之奈米孔隙含碳氧化矽(CDO)其介電係數約低於2.3，可以滿足下一世代之更快速訊號傳遞要求，有效降低金屬連線的電阻-電容延遲時間，CDO介電膜擁有非常好的熱隱定性，非常低的漏電流，非常高的介電崩潰強度(> 5MV/cm)，非常長的本質生命週期。然而其卻也擁有一些電氣不穩性現象，應用先前的金屬載子入射分析、介電極化現象分析和漏電載子入射分析，我們成功的解釋其電氣不穩定特性，結合和上述三種機制提出一合理物理模型解釋之，並可用來解釋其它所有低介電常數材料的電氣不穩定現象。 碳化矽(a-SiC)是一新發展出的低介電常數金屬擴散障礙層，它雖然擁有很好的阻抗金屬離子擴散能力，但是在分析此類介電質材料的電氣特性時，卻也發現了其它不正常現像，將a-SiC做成的「金屬/a-SiC/矽」電容結構在高溫長時間偏壓狀態下，出現了一些電性上的不穩定現象，如在電容-電壓量測時，出現的磁滯現象。為此進而分析出此電性不穩定之形成原因：介電質極化效應，和其它如低漏電流之載子入射傳導現象。此電性不穩定性質，出現在大部份的低介電常數材料，為此我們亦建立起一分析模型來解釋此現象。 本論文並討論a-SiC介電質和其它低介電常數材料如：CDO之高溫氧化現象及其晶圓回收應用。金屬擴散阻障介質a-SiC可於低至550度的環境中氧化，且其氧化模式亦可用Deal-Grove Model來描述。應用此中低溫之介電質氧化現象，吾人發明一新的晶圓回收方法。這些介電質材料於氧化完成後並不會造成後續矽基底氧化損耗，故只要經過氫氟酸(HF)溶液即可蝕刻去除，比起傳統工業應用化學機械硏磨方法(CMP)具有更快速更低成本之晶圓回收成效。 最後我們也討論了應用孔隙型旋塗式塗佈低介電常數材料Porous-SiLK於未來更新的導線連線觀念，討論其於更高頻的訊號傳輸下，運用現有金屬連線系統形成之金屬介電質結構的微帶線(Microstripline)於高頻的射頻(RF)或是微波(Microwave)下之介電質特性。討論以金屬導線設計之微帶線結構在傳遞高頻微波訊號(6GHz)時，導線之電阻、電容、電感、電導，及分析介質損耗和金屬損耗的效應，籍以分析在高頻訊號傳遞時之金屬導線的小訊號模型，有助於模擬研究之用，以取代傳統導線的電阻-電容結構模型。我們可以淬取Porous-SiLK在高頻訊號傳輸下的介電特性及損耗。藉由建立此一高頻分析方式，可應用分析其它低介電常數材料於高頻傳輸時之特性。

This dissertation studies the electrical characteristics of low dielectric constant (low-k) materials in back end Cu interconnects of integrated circuits (ICs). It also discusses the possibility of applying low dielectric constant film in high frequency signal transmission. The most mature low-k material, Fluorosilicate Glass (FSG) and several kinds of porous type low-k materials such as nano-porous Carbon-Doped-Oxide (CDO) and spin coated porous SiLK were investigated. In addition, low dielectric constant diffusion barrier amorphous silicon carbide (a-SiC) was also studied. FSG is a fluorine contained silicon glass. It can be deposited in a chemical vapor deposition (CVD) system and is most similar to the traditional dielectric (SiO2) used for integrated circuits. Although the dielectric constant of FSG is about 3.6 and is not low enough, it is the first low-k material that has been used for mass-production. Thus we used FSG to study possible metal ions diffusion behaviors on surface-processed low-k dielectric films during typical damascene process. A simple physical model was proposed to describe the observed metal ion diffusion behavior. Nano-porous CDO with very low dielectric constant (k < 2.3) is very suitable for next generation IC interconnect systems. It could effectively reduce the R-C delay. CDO film shows very good thermal stability, very low leakage current, very high dielectric strength, very good adhesion to TaN, and very long intrinsic lifetime. However, some electrical instability phenomena were observed. We developed a model consisting of dielectric polarization, carrier injections, and metal ion injection. This model can be used to explain most of the porous-type low-k materials’ electrical instabilities. CVD deposited a-SiC film is a low dielectric constant diffusion barrier. Although a-SiC film has a very good resistance to metal ions injections, we also found some unstable phenomena while characterizing its electrical characteristics. As an example, the metal/a-SiC/Si-substrate capacitor exhibits a hysteresis behavior under continuous C-V measurement. A physical model consists of dielectric polarization at high field and carrier injection at low field and high temperature was proposed. Because the electric field in IMD is always less than 0.5 MV/cm under normal operation, electrical instability will not be issue under normal operation. Since lots of low-k dielectrics were developed in these years. A universal wafer reclaim method is needed. We observed that a-SiC and CDO films can be easily oxidized at medium temperature and this oxidation follows the Deal-Grove model. Applying this oxidation behavior, a universal wafer reclaim method was invented : oxidation followed by HF etching. This wafer reclaim method could effectively reduce the reclaiming time and lower the cost in comparison with the traditional wafer polishing. Finally, we considered the future new interconnect concept in this thesis. We studied high frequency signal transmission behavior in a stripline structure with spin-coated porous-SiLK low-k film. We developed a method to extract micro-stripline’s parasitic parameters such as resistance, inductance, conductance, and capacitance from S-parameter measurements. These stripline parasitic parameters are useful to build up a more accurate interconnect small signal model than the traditional interconnect R-C based model. We also discussed the dielectric loss and interconnect metallic loss to realize the possible application of porous-SiLK at high frequency. With the same methodology, we could analysis other low-k materials’ high frequency behavior.