氟鈍化效應在高介電常數複晶矽層間介電層特性及可靠度研究

Abstract

根據半導體的微縮定律，隨著系統晶片（System on Chip, SOC）的半導體製造逐漸的微小化，持續降低CMOS元件中的閘極介電層及非揮發性記憶體(non-volatile memories)中的複晶矽層間介電層（inter-poly dielectric）厚度，以達到高元件密度及低操作電壓的趨勢。傳統的極薄二氧化矽介電層因量子穿遂效應而導致極大的直接穿遂漏電流，對整個元件產生了可靠度的問題。為了解決這嚴重的直接穿遂漏電流現象，本篇論文利用高介電常數材料（high-□）來替換傳統的二氧化矽。因為高介電常數材料在相同的等效二氧化矽厚度之下，有較大的實際物理厚度可以抵擋因量子的穿遂效應而產生的直接穿遂漏電流。 但使用高介電常數材料仍有遭遇其它的缺點。例如:在相同的二氣化矽電壓下，高介電常數材料有較高的界面狀態產生及較多的電荷補捉，這對於元件操做時臨限電壓的漂移有嚴重的影響。本篇論文利用高介電常數材料做為堆疊式快閃記憶體(stacked-gate flash memory)的複晶矽層間介電層上的穿隧介電層，並用氟摻雜的鈍化處理來討論對複晶矽層間電容的影響。在複晶矽層成長後以離子佈值的方式來植入氟摻雜，使氟原子在後續的高溫摻雜的活化過程中，使其擴散至複晶矽和複晶矽層間的高介電常數材料（high-□）介電層。利用氟的摻入探討有機金屬化學氣相沉積(metal organic chemical vapor deposition)所成長的三氧化二鋁(Al2O3)和二氧化鉿(HfO2) 來改進其可靠度和元件特性。

我們提出了以矽表面氟離子值入法(silicom surface fluorine implantation),將氟離子導入複晶矽和複晶矽層間的高介電常數材料（high-□）介面處。從實驗結果可充份證明，含氟摻雜的元件有較低的界面狀態產生，和較少的電荷補抓，對三氧化二鋁和二氧化鉿複晶矽層間電容，不論是漏電流、電子補捉率、崩潰電場和崩潰電荷，及熱穩定度，複晶矽層間電容的特性都有顯著的提昇。本篇論文中，非揮發堆疊記憶體的懸浮閘(Floating Gate,FG) 和控制閘(Control Gate,CG) 最好的氟劑量條件分別為5e13 cm-2 和5e15 cm-2。對於元件的可靠度和穩定性有明顯的改善。因此，等效氧化層厚度為5奈米及3奈米的三氧化二鋁和二氧化鉿將是45奈米及32奈米世代以下堆疊式快閃記憶體的絕佳候選複晶矽層間介電質。

According to the semiconductor scaling rule, for the semiconductor made of system on a chip (SOC) has become very little gradually, a continuously scaling of the gate dielectrics for complementary metal oxide semiconductor (CMOS) and inter-poly dielectrics (IPD) for electrically-erasable programmable read only memory (EEPROM) and stacked –gate flash memory is needed to achieve high density and low operation voltage trend. In tradition, the ultra-thin silicon dioxide (SiO2) which the quantum effect and then cause more directly tunneling current, which is the issue of the reliability in all devices. In order to solve seriously directly tunneling current, this dissertation is to apply the high dielectric constant materials to replace SiO2. Because high dielectric constant materials compare with SiO2 at the same equivalent oxide thickness (EOT), have thicker physical thickness which can resist directly tunneling current from quantum effect. But using the high dielectric constant materials still has experienced other problems. For example , high dielectric constant materials have higher interfacial states and charge traps, these will cause more serious threshold voltage shift when working device as the same voltage compare with SiO2.In this thesis, we used high-k materials serving as the IPDs and tunnel dielectrics (TDs) on the stacked-gate flash memories. The influence of fluorine passivation effects on IPD capacitance was investigated. At post-IPD deposition, we incorporate fluorine with fluorine implantation method which was subsequently diffused into the IPD and high-k materials of tunnel dielectrics. The objective of this dissertation was to apply the fluorine incorporation to discuss deposition aluminum oxide (Al2O3) and hafnium oxide (HfO2) with metal organic chemical vapor deposition (MOCVD) for improving reliability and device characteristics. We describe the characteristics of silicon surface fluorine implantation (SSFI) for IPD and high-k materials interface with incorporation of fluorine. By experimenting, we found that lower generation rate of interface states and lower charge trapping rate are observed for device with fluorine incorporated. For Al2O3 and HfO2 inter-poly capacitors, the sample exhibits optimal quality in terms of leakage current, electron trapping rate, effective breakdown field and charge-to-breakdown (QBD) and the thermal stability of high temperature, the IPDs characteristics result of improving effect significantly. In this thesis, we investigated the most effective fluorine dosage condition respectively is 5e13cm-2 and 5e15cm-2 on floating gate, (FG) and control gate, (CG) of the non-volatile stacked –gate flash memory. Thus enhances the reliability and the stability of high-k devices. As thin as 5nm and 3nm equivalent oxide thickness (EOT) of Al2O3 and HfO2 IPDs are suitable to meet the requirement of 45nm and 32nm generation stacked-gate flash memories respectively.