維特比解碼器於PACDSP平台之實作設計

Abstract

PACDSP為一個本國製且有效率之數位信號處理器平台，特別適合多媒體應用，在可取得之文獻中，僅有少部份有關通訊系統之應用實現於PACDSP平台上，本論文率先將維特比解碼器實作於PACDSP平台。維特比解碼器是通訊系統接收機內耗費最多資源的運算之一，因此，為了減少其在PACDSP平台上之運算時脈數，本論文採用了VLIW及SIMD架構，並針對記憶體及暫存器的使用進行良好的配置，實作一個數位系統廣播系統規格之高平行度軟判決維特比解碼器，本設計可在操作頻率為200MHz之運算速度下，每一個叢集可達到1Mbps之資料解碼速度。此外，本論文亦針對PACDSP平台實作通訊系統進行效率評估，並建議在PACDSP平台新增若干新特殊指令，以增進其運算效能。

PACDSP is an efficient native DSP processor suitable for multimedia applications. For telecommunication applications, little work has been done for their realizations on PACDSP in literature. This work is the first one to implement the Viterbi decoder on PACDSP. A Viterbi decoder consumes significant amount of resource in a receiver. Hence, for reducing the execution cycles on PACDSP, this work utilizes the techniques of VLIW, SIMD, memory collocation, and register allocation to implement a highly-parallel soft-decision Viterbi decoder for DVB system. This design can execute up to 1Mbps output data rate per cluster with operating frequency of 200MHz. Furthermore, this work also evaluates the efficiency of PACDSP in implementing communication systems, and suggests several new special instructions for PACDSP platform to enhance its executing performance.