高速電流引導式數位類比轉換器

Abstract

通訊系統裡大多數的資訊是在數位形態做處理，但是這些資訊要發射到介質中時，需要轉到 類比的形態再由載波傳送出去。可知，數位類比轉換器及類比數位轉換器是系統中必須要的 區塊。而這些轉換器是連接品質好壞的關鍵，經常限制了通訊系統的速度與精準度，因此高 頻寬與高動態範圍的轉換器是有強烈需求的。

本論文將著重在數位類比轉換器(Digital-to-Analog Converters, DACs)上，要達高速操作電流 引導式架構是被廣泛採用的，因其速度限制是來自於輸出端而非電路內部，因此有利於高速 操作。然而，非理想的電流切換限制了無雜散動態範圍(spurious-free dynamic range, SFDR) 的頻寬，當輸入之數位信號達高頻時無雜散動態範圍也急速下降。為了保持良好的高頻無雜散 動態範圍，此論文提出「數位式亂數歸零法(Digital Random Return-to-Zero, DRRZ)」。

為了實驗本論文提出的「數位式亂數歸零法」，吾人實現一個八位元、每秒十六億個取樣之 數位類比轉換器，使用九十奈米之互補式金氧半場效電晶體，此數位類比轉換器給定弦波輸入時， 其無雜散動態範圍優於六十分貝，直至輸入頻頻高達四點六億赫茲，且優於五十五分貝直到 輸入頻率為八億赫茲，功率消耗量為九十毫瓦。

當高解析度的電流引導式數位類比轉換器是必須時，電流源就得高度滿足匹配特性，其付出的代價 即為大面積，由面積引起的本質電容、雜散電容也變大因而導致頻寬下降，改善此現象的途徑為使用較小 面積的電流源。然而，小面積電流源將引起嚴重的不匹配，本論文提出一個背景校正技術來保確 高精準度。

為驗証本論文提出的背景校正理論，吾人實現一個十二位元數位類比轉換器，使用九十奈米金氧半場 效電晶體，且電流源面積只有理論值的四百分之一。此數位類比轉換器功率消耗為一百二十八毫瓦， 有效面積為一仟一百乘七百五十微米。操作速度可達每秒十二點五億個取樣。當頻率高達五億赫茲時， 此數位類比轉換器有優於七十分貝之無雜散動態範圍。

In communication systems, most of the information processing is performed in the digital domain, but the signal carrying the information must be transmitted using analog signals. Therefore, the use of digital-to-analog(DA) and analog-to-digital(AD) converters are unavoidable. Data converters are critical for connecting signals to the real world, often limiting the accuracy and speed of the overall system. As a result, wide-band high-dynamic-range converters are in high demand.

This thesis focuses on the Digital-to-Analog Converters (DACs). The current-steering structure has been widely used in high-speed DACs, since in this structure the main speed limitation comes from the output node, and high sampling speed is thus easily achieved. However, the non-ideal switching limits the bandwidth of spurious-free dynamic range(SFDR). The SFDR decreases rapidly with increasing input frequency. Therefore, Digital Random Return-to-Zero(DRRZ) is proposed for the high sampling rate current-steering DAC to maintain high SFDR at high frequency.

To demonstrate the proposed Digital Random Return-to-Zero technique, a CMOS 8-bit 1.6-GS/s DAC was fabricated in a 90 nm CMOS technology. The DAC achieves a SFDR better than 60 dB for a sinewave input up to 460 MHz, and better than 55 dB up to 800 MHz. The DAC consumes 90 mW of power.

In the design of high-accuracy current-steering DACs, current sources with high matching property are required and the penalty is large area. Intrinsic and parasitic capacitor loading also degrade the signal bandwidth. The way to reduce loading is using compact current cells. In this thesis, background calibration is proposed to correct the mismatch current caused by small dimension.

To verify the proposed background calibration algorithm, a 12-bit DAC was fabricated in 90nm CMOS technology and using compact current cells. The area of current sources are 1/400 of the required area which is designed for 12-bit resolution. The chip consumes 128mW. Active area is 1100x750um2. At 1.25GS/s sampling rate, the DAC achieves better SFDR than 70dB up to 500MHz input frequency.