應用於系統晶片之低功率全數位式時脈產生器

Abstract

隨著製程技術的進步以及電子產品功能需求的增加，系統晶片的複雜度日益增高。在複雜的系統晶片設計中，需要許多種類不同的時脈訊號以因應不同的功能需求。因此，如何設計適合於系統晶片的各種時脈產生器就成為一重要的議題。傳統上，時脈產生器常使用類比方式實現，但是類比時脈產生器於低供應電壓準位時面臨強大的設計挑戰，同時它有較低的系統整合度與較高的面積成本。相對於類比方式，全數位的實現方式則具有高系統整合度與低面積成本的特性，十分適合於系統晶片的應用。除此之外，在系統晶片應用中，功率和效能是設計時脈產生器最主要需要克服的問題。因此，本論文提出使用全數位的設計方案來實現多種應用於系統晶片的時脈產生器，並有效降低功率消耗與增進電路效能。 在全數位的時脈產生器設計中，最核心的電路模組為數位控制振盪器與延遲細胞元。數位控制振盪器與延遲細胞元的效能表現與功率消耗對全數位時脈產生器的整體效能表現有顯著與重要的影響。因此，本論文首先提出一低功率高效能的數位控制振盪器與延遲細胞元，而這樣的數位控制振盪器設計可同時應用於多種全數位時脈產生器之中。此數位控制振盪器使用粗調-微調的串接架構來提高操作頻率範圍同時維持高延遲精準度。粗調的部分使用分割延遲線的架構來節省不必要的功率消耗，細調的部分則使用遲滯延遲細胞元來減少電路的負載與複雜度進而減少功率消耗。因此，數位控制振盪器的整體的功率消耗可大幅降低同時維持高效能表現。 鎖相迴路是時脈產生器中最常見與最基本的一種。在具有功率管理功能的系統中，鎖相迴路需要能快速的提供已鎖定的時脈訊號，因此本論文接著提出具快速鎖定特性的全數位鎖相迴路。所提出的二階層快閃式時間數位量測轉換器能大幅縮短鎖定時間同時只需少量的硬體成本。除此之外，全數位展頻時脈產生器則是另一個常使用於系統晶片的電路，其作用為降低時脈訊號對系統的電磁干擾。本論文提出重排程片段三角調變的演算法來完成可程式化的展頻比率並同時保持對輸入時脈相位的追蹤能力。 在系統晶片中，記憶體是不可或缺的基礎元件。而其中雙資料速率記憶體因其高效能而廣為使用。由於雙資料速率記憶體控制器需要特殊的時脈控制訊號使雙資料速率記憶體能正確的工作，因此本論文提出以全數位延遲迴路與數位控制相位變換器為基礎的可調式時脈產生器，並可克服因長距離佈線所造成的延遲不匹配問題。而記憶體則需要同步映射延遲電路來解決內部因佈線長短不同而造成的時脈扭曲問題。本論文所提出的全數位式同步映射延遲電路使用邊緣觸發映射延遲細胞元以及使用高精確度延遲細胞元的微調延遲線來擴大可接受責任週期的範圍與縮小靜態相位誤差。 本論文所提出的全數位時脈產生器設計方案中，除了使用所提出的數位控制振盪器與各種設計技巧來提高效能與降低功率消耗，並且皆使用標準函式庫元件來實現硬體。因其具有的可移植性，它可如同軟矽智產一般的輕易將其設計轉換於不同的製程上。因此，所提出的全數位時脈產生器非常適合應用於系統晶片與系統層次整合。

hus, how to design the various clock generators for SoC applications becomes an important topic. Traditional clock generators are designed by analog approach. However, the analog clock generator not only encounters a high design challenge as supply voltage decreases, but also it is hard to be integrated into system design due to large area. In contrast to analog approach, all digital design approach is very suitable for SoC applications due to high portability and low design cost. In addition, power consumption and performance are major design considerations of clock generator in SoC applications. Thus, this work proposes a systematic all-digital design approach to implement various clock generators with high performance and low power for SoC applications. The kernel module of all-digital clock generators is digitally controlled oscillator (DCO) and delay cell. Because DCO and delay cell dominate the overall performance and power consumption of all-digital clock generator, this work proposes a high-performance and low-power DCO and delay cell that can apply to all kinds of all-digital clock generators for SoC applications. The proposed DCO employs a cascadable structure with coarse and fine-tuning stage to achieve high resolution and wide frequency range at the same time. The coarse-tuning stage utilizes a segmental delay line (SDL) to reduce redundant power, and the proposed hysteresis delay cell (HDC) can reduce the circuit complexity and loading of the fine-tuning stage to further lower down the power consumption. As a result, the power consumption of the proposed DCO can be reduced significantly while keeping high performance. The phase-locked loop (PLL) is the most essential type of clock generator. For the power management system application, PLL should provide the locked clock signal in a short time. Thus, this work proposes a fast-lock-in all-digital PLL (ADPLL) which employs a novel 2-level flash time-to-digital converter (TDC) to reduce lock-in time with low hardware cost. Besides, an all-digital spread spectrum clock generator (ADSSCG) that reduces the electromagnetic interference (EMI) effect is another important design in SoC applications. The proposed rescheduling division triangular modulation (RDTM) scheme can enhance the phase tracking capability and provide wide programmable spreading ratio at the same time. Memory is an essential component of SoC design. Double data rate (DDR) memories have been widely used for high-performance system in modern SoC designs to meet required data bandwidth. Because DDR memory controller needs specified clock and control signal to ensure the functionality and performance of data accesses, a tunable phase shift scheme based on all-digital delay locked loop (ADDLL) and digital control phase shifter (DCPS) has been proposed in this work to solve the delay mismatching issue. In addition, memory design utilizes the synchronous mirror delay (SMD) to eliminate the clock skew by wire delay mismatching. The proposed all-digital SMD (ADSMD) uses edge-trigger mirror delay cells to enlarge the input duty cycle range and fine-tuning delay line with high-resolution delay cell to reduce the static phase error. The proposed all-digital clock generators not only use the proposed DCO/delay cell and several design techniques to enhance performance and reduce power consumption, but also can be realized by standard cells in standard CMOS processes, making it easily portable to different processes as a soft intellectual property (IP). As a result, the proposed all-digital clock generators are very suitable for SoC applications as well as system-level integration.