適用於二維及矽穿孔三維積體電路之適應性功率管理設計

Abstract

本論文提出了包括一數位控制的線性電壓調節器及一適應性功率控制技術的適應性功率管理設計， 這些技術可獨立搭載於數位電路區塊上，也可同時採用以對於功率的控制有更大的彈性。 因類比式電壓調節器在製程不斷的演進下，設計越來越困難，因此本論文提出一數位控制可調變輸出的線性電壓調節器，並可支援電壓調變。採用聯電65奈米標準CMOS製程產出的雛型晶片量測結果顯示，其具有99.8%的電流效益率，靜態電流僅有164.5uA，而其控制系統所占之晶片面積約為300um^2。在論文中也為(所有)數位控制系統分析發展出一反應時間條件，以量化的方式描述控制系統之速度、輸出電壓的穩定度、以及所搭配去耦合電容之間的相互關聯，此反應時間條件可以做為電壓調節器之數位控制系統的設計準則，並可透過論文中提出的時間交錯式控制方法在這些參數之中做權衡設計。 另一方面，適應性功率控制技術可使目標電路盡量用完閒置的時脈以降低功率消耗。此技術的核心為一電路運作狀態偵測機制，可取代關鍵路徑複製技術來偵測電路的速度，此機制本質上即具有抵抗製程電壓及溫度變異的能力。透過動態的調整電源閘的大小，可以動態調整電路的運作速度，進而降低功率消耗。此技術的雛型晶片採用聯電90奈米標準CMOS 製程產出，相對於一32-bit乘法器來說，面積及功率的額外負擔均僅約1%，而此技術能夠達到平均56.5%的剩餘時脈使用率，12.39%的淨功率降低，並減少87.5%的漏電流。 本論文中的適應性功率管理設計可使用於二維以及矽穿孔三維積體電路的各種應用之中，同時也討論了具有溫度感知優先的功率管理設計原則，另針對矽穿孔三維積體電路的應用，本論文也提出了一多層式電源供應系統以因應三維積體電路應用所衍生的電源傳遞複雜性。

Adaptive power management designs are presented in this thesis including an all digital controlled linear regulator and an adaptive power control technique. Each one is essentially a stand-alone attachment for digital integrated circuit blocks while they can also be adopted jointly to have more flexibility on power control. Since the analog regulator design has suffered a lot from technology advancing, an all digital controlled variable output linear voltage regulator that supports voltage scaling is presented in this thesis. A test chip had been fabricated on UMC 65nm standard CMOS technology. The developed digital voltage regulator has a 99.8% current efficiency with only 164.5_A quiescent current. The area of the control system is about 300um^2. A response time constraint has been developed as well to provide a design guideline for (all) the digital control system. It describes the correlation between required speed of the digital control system, the output performance, and the size of the decoupling capacitor. A proposed time interleaving control can have trade-off between these parameters. The adaptive power control technique can utilize unused slack and reduce power. The switching state determination mechanism is the core technique replacing the critical path replica to detect circuit speed. It is intrinsically tolerant of PVT variations. The circuit speed can be altered by dynamically configuring the size of the power gating devices and hence reduce power. A test chip had been fabricated on UMC 90nm standard CMOS technology. The area and power overhead are both around 1% relative to a 32-bit multiplier. The proposed technique can achieve averages of 56.5% slack utilization, 12.39% net power reduction, and 87.5% leakage reduction. The adaptive power management designs are discussed on 2D planar and TSV 3DIC applications with temperature-aware power management methodology. A multi-layer power delivery structure is presented as well when going to TSV 3DIC applications.