積體電路電源線間具低漏電流之靜電放電防護電路設計

Abstract

隨著半導體製程的進步與發展，許多整合多功能的系統晶片已經成為各電子公司的產品研發主力，奈米電子時代的來臨提供積體電路更廣泛的設計平臺及更為前瞻的技術。許多積體電路產品已經使用奈米半導體製程技術進行量產，但其積體電路可靠度可能會成為奈米半導體製程中更需要考慮的問題，其中靜電放電(Electrostatic Discharge, ESD)防護已成為其中一個重要的可靠度指標。先進的奈米半導體製程雖然能有效地微縮元件尺寸進而提升電路運算效率，在半導體元件本身的特性卻會因尺寸過小產生許多微米製程中不需考慮之影響，如閘極透納電流(Gate Direct Tunneling Current)會產生嚴重的漏電而降低晶片的效能。因此在奈米製程中，全晶片靜電放電防護設計需達到高效率、高防護能力及低漏電流之特性。另一方面，由於晶片的操作電壓隨著製程演進持續下降以符合元件閘極氧化層可靠度及低功率消耗之需求，但是周邊電路的電壓卻未隨半導體製程的進步而降低，所以在扮演晶片輸入輸出媒介的混合電壓界面(Mixed-Voltage I/O Interface)上將會產生許多問題。因此要在此混合電壓電路加上其靜電放電保護電路，考量界面電壓轉換及可靠度等問題，如何仔細評估這些問題而設計出具有高的靜電放電防護能力的電路將是當今以及未來積體電路設計上的重要課題，隨著半導體製程進入奈米級製程之後，對積體電路設計產業更加重要。另外，隨著高壓功率積體電路製程(Bipolar-CMOS-DMOS, BCD)在面版驅動電路、電源供應器及電源管理等使用的普及化，對於使用在這些應用的輸出端以及當作靜電放電保護元件的高壓電晶體來說，其高觸發電壓及低持有電壓的特性將使得高壓積體電路的靜電放電防護能力不足，並有可能產生閉鎖效應(Latchup)或類似閉鎖效應(Latchup-Like)的危險。因此如何開發有效的靜電放電防護設計，將是這些高壓積體電路設計上很重要的課題，這個主題也隨著這些產業應用上的多元化而更趨重要。所以本論文分別針對了奈米製程應用、混合電壓界面電路以及高壓功率積體製程應用上的限制與困難作討論，並進一步設計出有效的靜電放電防護電路以適用在各相關應用之積體電路晶片。 為了提供適用於奈米製程，具低漏電的全晶片靜電放電防護設計，本論文提出一新型靜電放電箝制電路，利用矽控整流器(Silicon Controlled Rectifier, SCR)作為靜電放電保護元件，及靜電放電偵測電路採取基體觸發(Substrate Triggered)技術來提昇其靜電放電防護能力。矽控整流器不具有閘極氧化層可有效避免閘極透納電流。且在考量閘極電流存在的操作情況下，此新型靜電放電偵測電路可在正常工作時有效地降低其漏電流，此靜電放電防護電路已在65奈米互補式金氧半製程中實際被製作與驗證。其人體放電模式(Human-Body-Model, HBM)及機器放電模式(Machine-Model, MM)的靜電放電耐受能力可以達到 7kV及325V，於室溫在1V工作電壓下，其漏電流僅96nA。 為了提供有效的靜電放電防護電路於奈米製程下高低壓共容輸入輸出電路，本論文提出可耐高工作電壓之靜電放電箝制電路，用來保護可接受兩倍工作電壓訊號之共容輸出輸入電路。此可耐高工作電壓之靜電放電箝制電路利用低壓薄閘極氧化層元件來實現，並納入閘極電流作為低漏電流設計之重點。利用靜電放電匯流排及可耐高工作電壓之靜電放電箝制電路可有效地排放各種放電組合之靜電放電電流，以保護高低壓共容輸入輸出電路。此適用於1V/1.8V高低壓共容輸入輸出電路新型電路已在65奈米互補式金氧半製程中實際被製作與驗證。 為了應用於高整合度之積體電路系統中，利用N型金氧半場效電晶體(NMOS)阻隔的技巧之高低壓共容輸入輸出電路被設計用來接受三倍、四倍甚至五倍的操作電壓，本論文提出兩個利用低電壓元件所實現的可耐受三倍工作電壓之靜電放電防護設計，透過不同的設計概念達到基體觸發之效用，提供有效的觸發電流，以提升防護元件之靜電放電耐受能力。本論文所提出應用在1.2V/3.3V高低壓共容輸出入界面之靜電放電防護設計已經在130奈米1.2V互補式金氧半製程下實現並已在3.3V的操作環境下驗證。 在高壓功率積體電路製程技術中，擴散式金氧半電晶體(DMOS)被廣泛地使用於靜電放電防護元件。本論文以擴散式金氧半電晶體為基礎提出新型的靜電放電防護電路以提升防護元件之導通效能及靜電放電耐受度。在正常電路操作時，擴散式金氧半電晶體可偏壓於40V而其5V閘極氧化層不會受到可靠度問題，另一方面此電路可進一步設計以避免高壓積體電路發生閉鎖效應或類似閉鎖效應的危險。此電路已在0.35微米5-V/40-V高壓功率積體電路製程中實際被製作與驗證。 本論文分別針對了奈米金氧半導體製程特性、混合電壓界面電路以及高壓功率積體電路製程應用上的限制與困難作討論，並設計出低漏電、高效能、並且在正常工作時不會受到閉鎖效應危險的靜電放電防護電路，所設計的靜電放電防護電路均已在實際晶片上成功驗證，並有相對應的國際期刊論文發表與專利申請。

Continually scaling down the CMOS technologies into nanoscale generation imposes significant challenges in integrated circuit (IC) reliability, where electrostatic discharge (ESD) protection has become one of the major concerns. To meet such reliability specifications are necessary for IC product qualification. From the perspective of ESD, the similar gate oxide breakdown voltage and trigger voltage of MOSFET devices increased the design difficulty. Moreover, the secondary device characteristics of MOSFET have been considered in nanoscale CMOS generations. The most important impact for ESD is the gate direct tunneling current, which happens between the gate and silicon beneath the gate oxide, occurs while MOSFET implementing in a nanoscale CMOS process. Such gate tunneling current could induce a substantial fraction of overall leakage current in a chip. The traditional ESD protection circuit with a large gate oxide dimension suffers serious gate leakage issue. The on-chip ESD protection circuit in nanoscale CMOS process should be design with consideration of gate tunneling current to achieve a low standby leakage current during the normal circuit operation condition. During the ESD stress, the on-chip ESD protection circuit should provide efficient protection capability to assure the safety of the internal circuit which has a small gate oxide breakdown voltage in nanoscale CMOS process. For the mixed-voltage I/O interfaces with thin gate-oxide devices, the on-chip ESD protection designs will meet design difficulties, such as gate-oxide reliability constraints and undesired leakage current paths. In high-voltage Bipolar-CMOS-DMOS (BCD) technology, high-voltage transistors have been widely used for display driver ICs, power supplies, and power management ICs. The high-trigger-voltage and low-holding-voltage characteristics of HV transistor have been found to cause latchup or latchup-like failure and insufficient ESD efficiency. Therefore, how to develop an efficient on-chip ESD protection design is an important challenge for high-voltage IC products. In this dissertation, the ESD design constraints in nanoscale CMOS process, mixed-voltage I/O interfaces, and high-voltage CDMOS technology are presented. Furthermore, the novel design solutions for on-chip ESD protection circuit have been developed to meet the design constraints in such technologies and applications. To provide effective on-chip ESD protection with low standby leakage current in nanoscale CMOS technology, a new power-rail ESD clamp circuit by using the silicon controlled rectifier (SCR) device and ESD detection circuit with substrate-triggered technique is proposed. The SCR device without poly-gate structure has good immunity against the gate leakage current. The special ESD detection circuit is designed with consideration of gate current to reduce the standby leakage current. The new proposed design has been fabricated and verified in a 65nm fully-silicided CMOS process. The new proposed power-rail ESD clamp circuit can achieve 7kV in human-body-model (HBM) and 325V in machine-model (MM) ESD levels while consuming only a standby leakage current of 96nA at room temperature under 1-V bias. In order to protect the mixed-voltage I/O interfaces in nanoscale CMOS technology, a new high-voltage-tolerant ESD clamp circuit is proposed to protect the mixed-voltage I/O circuits for receiving signals with 2□VDD voltage level. The devices used in the high-voltage-tolerant ESD protection design are all low-voltage thin gate-oxide devices. The gate current of each thin gate devices in the high-voltage-tolerant ESD detection circuit has also been considered. By using the ESD protection scheme with the ESD bus and the proposed high-voltage-tolerant ESD clamp circuit, the mixed-voltage I/O circuit can be well protected. The new proposed circuit has been fabricated in a 1-V 65-nm CMOS process for experimental verification. In high integrated electronic system, the mixed-voltage I/O design with NMOS blocking technique is applied for receiving 3×VDD, 4×VDD, and even 5×VDD input signals without the gate-oxide reliability issue. In this dissertation, two new ESD protection design by using only 1×VDD low-voltage devices for mixed-voltage I/O buffer with 3×VDD input tolerance are proposed. Two different special high-voltage-tolerant ESD detection circuits are designed with substrate-triggered technique to improve ESD protection efficiency of ESD clamp device. These two ESD detection circuits with different design concepts both have effective driving capability to trigger the ESD clamp device on. These ESD protection designs have been successfully verified in two different 130nm 1.2-V CMOS processes to provide excellent on-chip ESD protection for 1.2-V/3.3-V mixed-voltage I/O buffers. In high voltage CDMOS technology, the high-voltage DMOS is widely used as on-chip ESD protection devices. The trigger voltage of the high-voltage devices is too high to protect the output buffer. Such characteristics will cause the high-voltage DMOS susceptible to the latchup or ESD danger in the practical applications. To greatly improve ESD performance of the high-voltage DMOS devices, gate-driven and substrate-triggered circuit techniques are applied. The proposed gate-driven and substrate-triggered ESD protection circuits have been successfully verified in a 0.35-□m 5V/40V bipolar CMOS DMOS (BCD) process. In addition, the power-rail ESD protection design can be also achieved with stacked structure to protect 40-V power pins without latchup issue in the smart power ICs. In this dissertation, the novel ESD protection circuits have been developed for nanoscale CMOS process, mixed-voltage I/O interfaces and high-voltage BCD process with high ESD robustness. Each of the ESD protection circuits has been successfully verified in the testchips. The proposed ESD protection circuits in this dissertation can achieve the benefits of low standby leakage current, high ESD performance, and latchup-free characteristics for whole chip ESD design in CMOS ICs.