标题: | 高压积体电路之可靠性验证与改良 Reliability Verification and Improvement of High Voltage Integrated Circuit (HVIC) |
作者: | 曾恕鹏 Tseng, Su-Peng 张翼 Chang, Yi 工学院半导体材料与制程设备学程 |
关键字: | 系统层级的 ESD;高压积体电路;可靠性验证与改良;故障分析;静电破坏;高温操作寿命试验;Bipolar, LDMOS;LVMOS ,HVNMOS;ESD, HTOL;SL ESD;Failure Analysis |
公开日期: | 2010 |
摘要: | 摘要 高压电源管理积体电路, 近年来被广泛使用在白光发光 二 极体 , 液晶显示器驱动器 和汽车电子等领域. 在高效能高可靠度的要求下, 采用 BCD 晶片制程 ( BCD: Bipolar, CMOS and LDMOS) 是目前最普遍的. 在低成本的考量下 , 每一个晶片尽可能缩小 , 封装也使用成本最低廉的封装型态 (例如SOP, SOT等等). 所以如何提供适足的散热功能,充份的静电防治能力变成不可或缺的工作. 在高压制程部份, 近几年研究及应用的资讯更为热络 . 但是都较局限于元件与制程的范围.对于产品层级,系统层级的可靠性研究与应用的论文却很少见. 本论文是以高压电源管理积体电路为样本, 研究低压,高压及高电流(例如LVNMOS, HVNMOS, LDNMOS)元件的特性对此产品的影响 ,及探讨适当的高温操作寿命试验 ( HOLT )的方法, 并研究此产品系统层级的 ESD的可靠度. 本论文的实验结果显示在 ESD 保护部份,修改元件结构,制程及修改封装打线型态后,充分提升了产品层级抗ESD能力. 在高温操作寿命试验部份,找到使用85℃提高 2V 的电压为加速因子可以有效的进行高压高电流IC的可靠度试验. 在系统层级的ESD保护部份,确认了对过载电性冲击(Over Electrical Stress), 必须做适当的隔离. 对 LED 阳极的焊点与LED散热板的隔离空间进行研究, 确认了隔离空间 > = 4mm 是必须的 Abstract High Voltage Integrated Circuit (HVIC) is popularly used in the fields of LCD controller, white LED Driver and Mobile Electronics at present. For high reliability consideration, the complex process as BCD (bipolar, CMOS and LDMOS) process is introduced worldwide. For cost down purpose, the chip size is reduced as small as possible and the low cost package solutions as SOP, SOT...etc are selected. So the key works in this study are to get enough power dissipation with high ESD robustness in the compact space. This thesis uses a 42V 1A BCB HVIC to study the ESD robustness at product level and system level, and also studies the methodology of High Temperature Operating Life (HTOL) test for the high power management IC. Some specific results are (1) Significantly upgrade Product Level ESD robustness by way of changed device structure (Channel Length), skipped LDD process and wire bonding type of package. (2) After the experiments, we find HV IC performance, the reasonable experiment temperature is 85℃. To get enough accelerated factor, the accelerated factor of high voltage up is easy to handle with no extra cost in the new experiments. (3) Dynamic resistance of board level ESD protector will impact the internal circuit when the extra huge power is discharged. So the isolated space (between LED Anode soldered point and LED heat sink) is studied and verified. 4mm space can pass SL ESD 8KV test which is the minimum distance requirement in system level ESD. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT079375506 http://hdl.handle.net/11536/40693 |
显示于类别: | Thesis |
Files in This Item:
If it is a zip file, please download the file and unzip it, then open index.html in a browser to view the full text content.