在時序良率的限制條件下之統計型靈敏度的邏輯閘置換方法

Abstract

當製程技術下降到奈米級尺度領域，製造的變化成為電路延遲越來越重要的部分。為電路最佳化使用邊界模型(corner model)分析用過度不利的解嚴重過度限制系統。因此，我們需要統計型解決時序分析和最佳化的問題。考慮到空間相互關係(spatial correlations)，這篇論文提出一個統計型置換(sizing)方法最佳化對規定電路的邏輯閘滿足時序良率(timing yield)限制條件。利用主要成分分析 (principal component analysis)將通道長度(channel length) ，氧化層厚度(oxide thickness)和溫度這類具有空間相互關係隨機過程的物理和環境因素的參數轉換成一組無相關性的隨機變數。在先進的統計型靈敏度架構尺度包含全域參數，區域參數和邏輯閘的面積，置換問題的邏輯閘可以被有效地做最佳化。實驗結果顯示電路的面積大約可以減少平均9.9%透過被提出的統計型靈敏度架構方法。

In the nano-scale of semiconductor technology, manufacturing variations become an increasingly significant part of circuit delay. Using corner model analysis for circuit optimization severely over-constrains the system in solutions with excessive penalties. Therefore, we need statistically analyze the circuit timing and optimize the design task. Considering the spatial correlation, this thesis presents a statistical sizing approach to optimize gates for a given circuit with satisfying the timing yield constraints. Firstly, the random processes of physical and environmental factors parameters such as the channel length, oxide thickness and temperature with spatial correlations are transformed to a set of uncorrelated random variables by using the principal component analysis. Then, with a developed statistical sensitivity based metric involving global parameters, local parameters and gate area, the gate sizing optimizing problem can be done effectively. The experimental results show that the area usage of circuits can be decreased about 9.9% in average by the proposed statistical sensitivity based method.