運用 NCL 設計之自時有限場乘法器

Abstract

在有限場的數學運算中，乘法運算的複雜度最高且最耗時間。在這個領域中， 由 Massey 和 Omura 所提出的一個基於正規基底的乘法演算法是一項非常重要的貢獻。採用正規基底的一個最大優勢在於元素的平方運算只要循環的執行向右位移即可。

在這篇論文裡，使用NCL開發出一個自時的Massey-Omura乘法器。實驗顯示 初版的 4-bit ×4-bit 電路設計可以節省63%的功率消耗而擴張後的23-bit × 23-bit實作也能節省49%的功率消耗。本電路設計除了顯示其低功率消耗的優點之外，它還適用於發展更大寬度的乘法器。而這些要歸功於 Massey-Omura 乘法器的規律性架構和非同步電路的高度組合性質。

In arithmetic operations of finite field, multiplication is the most complex and time consuming operation. An important advance in this area is the Massey-Omura algorithm, which is based on the normal basis representation of the field elements. One advantage of normal basis is that the squaring of an element is executed by a cyclic right shift.

In this thesis, a self-timed Massey-Omura multiplier is developed using the NULL Convention Logic paradigm. The simulation shows the initial 4-bit ×4-bit design saved about 63% power and the expanded 23-bit ×23-bit implementation saved about 49% power as well. This design demonstrates that it has advantage of low power consumption, and it is readily utilized for larger width operands. All is credited to the regular architecture of Massey-Omura multiplier and high composability of asynchronous circuits.