先進加解密標準演算法硬體電路之實現

Abstract

先進加解密演算法已成為全世界密碼學公認的標準。在先進加解密系統研究分為軟體及硬體電路。本論文我們著重高速度電路為主要目標並採平行架構。 在本論文中，提出一個新的方法來實現先進加解密密碼系統之架構。整個先進加解密密碼系統電路及金鑰擴展電路，利用查表法取代複雜運算電路。在硬體實現我們利用唯讀記憶體、互斥或閘及多工器來實現電路。首先，在功能驗證模擬方面，我們以MATLAB語言程式來模擬。其次，在RTL模擬驗證方面，我們利用verilog HDL建立系統並加以驗證。在電路合成部份，我們使用聯電0.13um CMOS標準元件庫來合成我們的電路。在加密部份，對於資料路徑128位元，工作頻率最高可達204MHZ左右，頻寬輸出2.6Gbps,總閘數273k; 在解密部份，對於資料路徑128位元，工作頻率最高可達200MHZ左右，頻寬輸出2.56Gbps,總閘數461k。

The advanced encryption standard (AES) algorithm has been standardized in cryptography all over the world. The research of AES focus on two areas: One is the software simulation and the other is the hardware implementation. In this thesis, a table-based high-speed AES ASIC design is proposed with a parallel structure. A look-up table approach instead of complicated circuits is exploited to realize the AES algorithm, included the encryption, the decryption, and the key-expand, whose circuits are implemented by ROM table, XOR gate, and multiplexer. First, we use Matlab platform to do AES function simulation. Then, we use Verilog HDL to build and verify the AES system in RTL level. Finally, the proposed HDL code is synthesized with UMC 0.13um CMOS process. In the encryption with the 128 bits data path, it shows that the operating frequency can be over 204MHz, to provide the 2.6Gbps data throughput. The total gate counts is about 273k. Moreover, the complexity of decryption is 461k gates whose clock rate can achieve 200MHz to supports the 2.56Gbps throughput in the 128 bits data path.