標題: | 一個0.8-V低功率類比前端積體電路應用於生醫訊號紀錄 A 0.8-V Low Power Analog Front-End IC for Biomedical Signal Recording |
作者: | 高碩廷 Shuo-Ting Kao 蘇朝琴 Chau-Chin Su 電控工程研究所 |
關鍵字: | 生物電位放大器;穩定截波;低電壓;低功率;數位類比轉換器;連續近似暫存器;bio-potential amplifier;chopper-stabilized;low-voltage;low-power;analog-to-digital converters;successive approximation registers |
公開日期: | 2008 |
摘要: | 為了醫療上的用途,可攜帶的生醫訊號量測系統的需求越來越大。我們希望病人可以攜帶輕巧的監控裝置以做長時間的監控。本專案提出一個0.8-V低功率,可程式化的CMOS類比前端積體電路應用在生醫訊號測量。我們的設計能夠處理心電圖,肌電圖,以及腦波訊號,並且利用chopper-stabilized與交流回授電路技巧阻隔電極片的直流偏移,共模雜訊,以及1/f雜訊。儀表放大器的input-referred noise floor為57 nV/sqHz 以及4.7的noise-efficient factor (NEF)。另外,可程式化放大器的電壓增益以及頻寬可以透過數位介面控制,實現上容易與DSP整合。考慮到放大器部分有70dB的動態範圍,因此整合一個低電壓低功率的連續近似暫存器類比數位轉換器。該類比數位轉換器有0.09 pJ/Conv.step,在取樣頻率為2.67 KS/s 下有63dB的訊號對雜訊與失真比 (SNDR),以及0.31μW的功率消耗。工作電壓範圍0.4-0.8V。前端放大器功率消耗是1.84μW。總功率消耗是3.9μW (不包含輸出緩衝器以及偏壓電路)。所提出的電路架構將被實現在TSMC CMOS 0.18 m的製程,其晶片面積為1.12mmX0.36mm (不包含PAD) For medical purposes, there is a growing demand for portable bio-potentials signals systems. We hope that patients can wear the small-size and light-weight devices for long-term monitoring. A 0.8-V low power programmable CMOS analog front-end IC for biomedical signal acquisition is presented. Our design deal with Electrocardiogram (ECG), Electromyogram (EMG), and Electroencephalogram (EEG) signals, while reject DEO (Differential Electrode Offset), common-mode disturbance, and solve flicker noise by chopper-stabilized technique with an AC feedback circuit. The instrumentation amplifier achieves 57 nV/sqHz input-referred noise floor and the noise-efficient factor (NEF) of 4.7. The programmable gain amplifier (PGA) sets voltage gain and bandwidth via digital interface, which could be integrated with DSP easily. Considering that the amplifier provides 70dB dynamic range (DR), a 11-b low-voltage low-power successive approximation register analog-to-digital converter (SAR ADC) is integrated. The SAR ADC circuit achieves Figure of Merit (FOM) of 0.09 pJ/Conv.step, a signal-to-noise-and-distortion ratio (SNDR) of 63dB at sampling rate of 2.67KS/s and power consumptions of 0.31μW. The supply voltage range is from 0.4V to 0.8V. The power consumption of the front-end amplifiers is 1.84μW. The total power consumption is 3.9μW (output buffer and biasing circuits are excluded). The chip is realized in TSMC 1P6M 0.18μm CMOS process. The active die area is 1.12mmX0.36mm. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT079512529 http://hdl.handle.net/11536/41083 |
顯示於類別: | 畢業論文 |