完整後設資料紀錄
DC 欄位語言
dc.contributor.author彭嘉笙en_US
dc.contributor.authorChia-Sheng Pengen_US
dc.contributor.author溫□岸en_US
dc.contributor.authorKuei-Ann Wenen_US
dc.date.accessioned2014-12-12T01:24:49Z-
dc.date.available2014-12-12T01:24:49Z-
dc.date.issued2005en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT008711617en_US
dc.identifier.urihttp://hdl.handle.net/11536/41112-
dc.description.abstract本論文針對應用於無線通訊系統之正交頻分多工(OFDM)技術,考量實作通訊系統傳輸的背景,包含通道、射頻以及傳輸規格,討論無線傳輸通道的影響效應和模型的建置方法、採用直接轉換的射頻架構所造成的非理想效應、基頻與射頻的相關介面討論,以及不同傳輸規格之設計考量。並針對無線區域網路所需之規範,提出相關之偵測、估計、同步、等化與解調等演算法及其效能分析,研究成果係針對不同通道與射頻效應所需,包含封包偵測(Packet Detection)、自動增益控制(AGC)、時脈偵測(Symbol Timing Detection)、載波頻率漂移(CFO)的估計與補償、通道的估計與等化、以及頻域上的相位追蹤等部分。在架構上提出以雙模座標旋轉數位計算器(CORDIC)為核心的設計,整合與簡化內部接收器(Inner Receiver)所需所有同步與等化之電路,針對多徑通道所造成的衰減效應,提出採用通道狀態資訊(CSI)之Demapping設計,有效降低所需的平均訊雜比以增加傳輸距離,並提出符合無線區域網路基頻的完整設計,從傳送端、前端接收器、內部接收器、FFT到外部接收器,有效降低全部的接收延遲至280 cycles,低於4個OFDM symbols的長度,以提高有效的傳輸量,經0.18um CMOS製程的cell library合成,共約42.4萬等效邏輯閘,且全部電路毋須使用RAM的設計,有利於未來整合於SOC的設計。在模擬與驗證考量上,提出以應用整合平台,模擬通道、射頻等環境,並納入Verilog實作電路的共同模擬,驗證實作系統的傳輸品質並有利於系統內部資料流與控制信號的偵錯工作,經由模擬與效能分析,以及實作系統針對傳輸品質與信號偵錯等驗證,得到8種實際電路的傳輸率及其效能結果,經由相關比較,可證實為高效能的設計以及其採用CSI對抗多徑通道的接收能力。zh_TW
dc.description.abstractThe dissertation presents a comprehensive design of OFDM transceiver for wireless applications, including system consideration, receiver technology, architecture, and evaluation. Wireless channel environments and RF nonideal effects have been considered for OFDM transmission. Novel methods for building wireless channel models have been introduced, including of delay spread interpolation and fader generators. The interface between baseband and RF, and the consideration over different transmission specifications have been also presented. For Wireless LAN system requirement, several receiver technologies are proposed for solving the effects caused from channels and RF environments, including packet detection, automatic gain control, symbol timing detection, detection and compensation of carrier frequency offset, channel estimation and equalization, and frequency-domain phase tracking. For implementing a baseband transceiver which accommodates to Wireless LAN systems, an architecture based on a dual-mode CORDIC module is proposed to integrate and reduce calculations of synchronization and equalization in the inner receiver; moreover, for some subcarriers suffering from severer attenuations under frequency-selective fading channels, a novel demapping method which adopts channel state information (CSI) and combines with OFDM equalizer is presented to decrease average SNR and increase transmission distance. The full implementation of baseband transceiver comprises transmitter, front-end processing, inner receiver, FFT/IFFT, and outer receiver, with total receiving latency as 280 clock cycles, less than 4 OFDM symbols duration, and with total complexity as about 424K equivalent gate count, benefiting in SOC integration by avoiding any usage of RAM components in the design. An integrated simulation platform is introduced with abilities to co-simulate channels and RF environments with practical Verilog codes for evaluating transmission performances over AWGN and multipath fading channels. According to simulation and evaluation results, 8 kinds of transmission rates with their required SNR and packet error rate (PER) are proposed and compared to prove the performance of the OFDM transceiver design.en_US
dc.language.isoen_USen_US
dc.subject正交頻分多工zh_TW
dc.subject無線通訊zh_TW
dc.subject傳收器zh_TW
dc.subject無線區域網路zh_TW
dc.subjectOFDMen_US
dc.subjectwireless communicationen_US
dc.subjecttransceiveren_US
dc.subjectwireless LANen_US
dc.title無線應用之正交頻分多工傳收器設計zh_TW
dc.titleOFDM Transceiver Design for Wireless Applicationsen_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
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