應用於超寬頻系統之低雜訊放大器與混波器設計

Abstract

本篇論文主要是利用標準0.18µm CMOS製程設計應用於超寬頻系統前端接收器之低雜訊放大器和混波器積體電路。在第一顆晶片裡，適用於接收端超寬頻系統之寬頻放大器被設計與分析。我們利用負回授電阻達到寬頻之輸入輸出組抗匹配以及自偏壓。實際量測結果顯示此一放大器在0.1GHz 到 6.6GHz頻率下有著最高功率增益(S21) 6.2dB，輸入返回損耗(S11)及輸出返回損耗(S22)小於-10 dB，以及平均雜訊指數8.1dB，此電路消耗之功率為16.2mW。 第二顆晶片中，我們利用柴比席夫濾波器來達到寬頻匹配，設計超寬頻系統接收器第二級之混波器，並在轉導級和混波級中間加入電感來使高頻的增益增加。實際量測結果顯示此寬頻混波器在3~8GHz有最高的轉換增益(Conversion Gain) 7.4dB，輸入返回損耗(S11)小於-4dB，平均IIP3為+3.4dBm，最小雜訊指數7.1dB。此電路消耗功率為11.8mW。

This thesis aim is to design an ultra wideband low noise amplifier and mixer in the UWB receiver system using standard 0.18um CMOS process. In first chip, an ultra wideband low noise amplifier is analyzed and designed in UWB system. We employ the negative feedback resistor to achieve input, output broadband matching. In the measured data, we show the maximum power gain is 6.2dB and input matching (S11) and output matching (S22) are less than -10dB from 0.1GHz to 6.6GHz. The average noise figure is 8.1dB. The total power consumption is 16.2mW. In second chip, we design a mixer which is the second stage of the UWB system. In this design, we use the chebyshev filter to achieve 3~8GHz broadband matching. And an inductor adds to between transconductance stage and switching stage which improve the high frequency gain. The measured result shows the highest conversion gain is 7.4dB at 3~8GHz band. Input return loss is less than -4dB. The average iip3 is +3.4dBm. The minimum noise figure is 7.1dB. The total power consumption is 11.8mW.