超大型積體電路製程之側壁間隔物蝕刻之改善

Abstract

本論文利用田口直交實驗法搭配較靈敏的終點偵測器來開發一新的製程程式,及開發一電性量測方式來測量側壁間隔物大小,來改善元件性能。 隨著晶片製程線寬越來越小,有越來越多的挑戰需克服,所以也開發出好多新的製程技術，其中側壁間隔物即是一例，它可用來當汲極/源極 LDD implant 的自我調校光罩,也可預防汲極/源極重疊，也可降低熱電子效應。由此可見此一道製程之重要性。本論文由田口直交實驗法中，發現於低壓低氬氣流量時，可有效改善側壁間隔物蝕刻之均勻度。 另外如何快速正確監測偌大晶圓上每個位置的側壁間隔物大小，以利後續分析改善元件性能，也是當下重要課題。本論文成功地利用基本電阻原理R=Rs*L/W ，由量得的電阻推算出側壁間隔物之寬度。

A procedure based on Taguchi methods and integrates more sensitivity EPD to develop a new etch recipe, and provide an electrical measurement method for monitoring the sidewall spacer width. The sidewall spacer has been used extensively in conventional CMOS processing, leading LDD (lightly-doped drain) formation to less hot carrier degradation allowing self alignment to prevent S/D short in the salicide process. In this thesis, we figures out by optimizing etch parameter with low pressure and Ar flow can be improved etch uniformity effectively. Creating a fast and correct measurement process for every die SW width to improve device performance is an important topic. In this thesis, we successfully derivate an equation to predict SW width from resistor measurement.