H.264/AVC可調性視訊編碼之分析與框內編碼器設計

Abstract

幾十年來，各式的視訊編碼規格被開發用以滿足人類對視訊的需求：高解析度、高畫質、高播放速率等。和之前的標準相比，H.264/AVC可在相同的資料量下提供更高的視訊品質。而作為H.264/AVC的延伸，可調性視訊編碼被設計用來以單一編碼端滿足多重解碼端的資料需求，接收端可依本身的頻寬及系統處理能力，自固定的資料流擷取相對應的部分予以重建視訊。 由於在H.264/AVC的基礎上建構，可調性視訊編碼的複雜度遠大於前者。因此在維持或少量增加複雜度及系統規格的前提下，設計一個可支援高效能的可調性視訊編碼器，是項極富挑戰性的議題。本篇論文藉由一項關於可調性視訊編碼器的記憶體分析、一種框內編碼的快速演算法，以及一個可調性視訊框內編碼器的實作，解決了此一問題。 首先，一項關於可調性視訊編碼的記憶體分析將被整理歸納，藉由選用最適合的編碼流程，可得到最低的記憶體使用量及頻寬。而在導入一些改善方法的幫助下，以增加8.3%內部記憶體的容量，再省下超過一半的外部記憶體頻寬。 其次，本篇論文提出一種框內編碼的快速演算法，利用整數離散餘弦轉換或哈達瑪轉換之結果，推測區塊的紋路，並藉此以選擇較少的候選模式做決策。在可接受的效能損失下，有效縮短約一半的編碼時間。 最後，一個結合快速演算法，可提供三種畫質的可調性視訊框內編碼器被實作出來。以巨圖塊層次的管線化架構進行編碼，避免了閒置時間並增加資料輸出量；此外在整體系統排程的規劃下，利用各元件的共用性，有效節省硬體資源。在135MHz的工作時脈之下，此編碼器每秒可處理超過59萬4千個巨圖塊，相當於60張HD 1080p、SD 480p以及CIF之總和。 簡而言之，本篇論文對於可調性視訊編碼之貢獻有三：其一是關於可調性視訊編碼之系統性的記憶體分析，其二是框內編碼的快速演算法，最後是一個可調性視訊框內編碼器的實作，藉低複雜度的計算及可接受的硬體成本，滿足在多重解析度下三種畫質的需求。

For recent decades, many video coding standards have been developed to satisfy the demands of video: high resolution, high quality, and high frame rate. Compared to previous standards, the state-of-art coding standard, H.264/AVC, can provide higher video quality by the same data transfer rate. As an extension of H.264/AVC, scalable video coding (SVC) is designed to satisfy multiple demands from data receivers by a single encoder. A receiver extracts the fixed bit-stream according to the bandwidth and processing ability itself, and reconstructs the video. Constructing on the fundamental of H.264/AVC, the complexity of SVC is much higher than former. Hence, it is full of challenge to design an SVC encoder to support high performance, with the same or slightly increased complexity and system requirement. In this thesis, that issue can be solved through a memory analysis on SVC encoder, a fast intra prediction algorithm, and the implementation of SVC fast intra encoder. At first, the memory analysis of SVC encoder will be presented. Through choosing the most suitable encoding method, the system would enjoy the minimal memory usage and bandwidth. Furthermore, by the aid of some improvement method, over the half of the external memory bandwidth can be saved with 8.3% increase in internal memory storage. Then, this thesis proposed a fast intra prediction algorithm. The texture of a block can be predicted by observing the result of integer discrete cosine transform or Hadamard transform. Thus, the total encoding time can be shortened to the half effectively, by selecting fewer mode candidates in mode decision, with acceptable performance loss. Last, an SVC encoder with 3 quality layers, combined with fast intra prediction algorithm is implemented. It operates under the pipeline architecture in macro-block level to avoid time idling and to increase data throughput. Besides, by the scheduling of the system, components are reused for effective hardware resource saving. This encoder processes more than 594k macro-blocks per second, which is equivalent to the summation of 60 HD 1080p, SD 480p, and CIF frames under the 135 MHz working frequency. In brief, to SVC, the contributions of this thesis can be divided by three parts: the first is the analysis for SVC encoder in system level; the second is a fast intra prediction algorithm; the third and the last is the implementation of an SVC intra encoder. With the low complexity computation and acceptable hardware cost, it satisfies the demands for three video qualities in multiple resolutions.