| Title: | SYSTOLIC FLOW |
| Authors: | TSAY, JC YUAN, S 資訊工程學系 Department of Computer Science |
| Issue Date: | 1-Mar-1990 |
| URI: | http://hdl.handle.net/11536/4177 |
| ISSN: | 0743-7315 |
| Journal: | JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING |
| Volume: | 8 |
| Issue: | 3 |
| Begin Page: | 286 |
| End Page: | 291 |
| Appears in Collections: | Articles |
- DATA FLOW REPRESENTATION OF ITERATIVE ALGORITHMS FOR SYSTOLIC ARRAYS / JEN, CW;KWAI, DM
- 用以設計與驗證韻律陣列之一種數學表示法 / 袁思;YUAN, SI;蔡中川;CAI, ZHONG-CHUAN
- 高速度和低複雜度公匙密碼系統之律動架構設計 / 蔡維昌;Wei-Chang Tsai;王聖智;項春申;Sheng-Jyh Wang
- 基於心臟收縮陣列之RBF類神經網路VLSI設計 / 郭俊宏;Chun-Hung Kuo;張志永;Jyh-Yeong Chang
- ON THE DESIGN OF VLSI ARRAYS FOR DISCRETE FOURIER-TRANSFORM / LIU, CM;JEN, CW
- REDUNDANCY DESIGN FOR A FAULT TOLERANT SYSTOLIC ARRAY / WANG, JJ;JEN, CW
- Two systolic architectures for modular multiplication / Tsai, WC;Shung, CB;Wang, SJ
- ON EQUIVALENT SYSTOLIC DESIGNS OF LU DECOMPOSITION AND ITS ALGEBRAIC REPRESENTATION / HOU, YC;TSAY, JC
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