Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 曾劭學 | en_US |
dc.contributor.author | Tseng, Shao-Hsueh | en_US |
dc.contributor.author | 林大衛 | en_US |
dc.contributor.author | Lin, David-W | en_US |
dc.date.accessioned | 2014-12-12T01:27:23Z | - |
dc.date.available | 2014-12-12T01:27:23Z | - |
dc.date.issued | 2009 | en_US |
dc.identifier.uri | http://140.113.39.130/cdrfb3/record/nctu/#GT079611659 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/41784 | - |
dc.description.abstract | 本篇論文在於研究IEEE 802.16e OFDMA 所訂定的迴旋渦輪 碼(CTC)系統並實現在數位訊號處理器(DSP)。闡明迴旋渦輪碼的 雙二位元循環遞迴系統迴旋(duo-binary CRSC)編碼以及利用最大 對數事後機率(max-log-MAP)進行BCJR (Bahl `Cock `Jelinek 和 Raviv 四位研究者做為命名)解碼演算法。我們利用C 語言驗證系統 演算法上的正確性,以及補償max-log-MAP 導致的效能損失,並在 加成性白色高斯通道下模擬了各種調變。 接著在TI C6416 DSP 平台,我們改變格子圖順序,以及利用DSP 內建函式達到平行運算,並且有效改善解碼器的運算速度。原始解碼 器的部分僅可達到約每秒800K 位元的處理速度,改善後解碼器的速 度增進約2倍,進而可以達到每秒1500K 位元的處理速度。 | zh_TW |
dc.description.abstract | The focus of this thesis is the research of the convolutional turbo code (CTC) defined in IEEE 802.16e OFDMA and implement on the C6416 DSP. We explain the duo-binary circular recursive systematic convolutional encoding (duo-binary CRSC) and use BCJR decoding algorithm by max-log-MAP. We employ the C program to insure the correctness of our algorithm and compensate the performance loss by max-log-MAP, furthermore, simulate the CTC for different modulations in AWGN. Then, we implement on TI C6416 DSP, changing trellis order and using intrinsic function to achieve parallel operation. Therefore, we improve decoder operation speed efficiently. For original decoder just can achieved a processing rate of 800 Kbps . For improved decoder , which is approximately 2 times speed up in decoding rate. Therefore, the decoder can achieve a further data processing rate of 1500 Kbps. | en_US |
dc.language.iso | zh_TW | en_US |
dc.subject | 迴旋渦輪碼 | zh_TW |
dc.subject | convolutional turbo code | en_US |
dc.title | WiMAX 迴旋渦輪碼技術與 數位訊號處理器實現 | zh_TW |
dc.title | WiMAX Convolutional Turbo Code Technology and Digital Signal Processor Implementation | en_US |
dc.type | Thesis | en_US |
dc.contributor.department | 電子研究所 | zh_TW |
Appears in Collections: | Thesis |
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