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dc.contributor.author詹茗皓en_US
dc.contributor.authorChan, Ming-Haoen_US
dc.contributor.author鄒應嶼en_US
dc.contributor.authorTzou, Ying-Yuen_US
dc.date.accessioned2014-12-12T01:27:33Z-
dc.date.available2014-12-12T01:27:33Z-
dc.date.issued2009en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT079612515en_US
dc.identifier.urihttp://hdl.handle.net/11536/41833-
dc.description.abstract本論文研製具負載適應增益調適混合信號控制之邊界模式功率因數修正(critical-mode power-factor-correction, CRM PFC)交-直流轉換器,可應用於中低功率電子設備如:可攜式電子產品或照明設備。本文所研製的混合信號控制其中電流迴路使用類比方式實現,電壓迴路則以數位方式實現。本文並提出負載適應增益調適(load adaptive gain adjustment)以及帶拒濾波器(notch filter)於數位電壓迴路,使系統輸出電壓可達到最佳動態特性且仍可使輸入電流具備低總諧波失真(total-harmonic-distortion, THD)以及高功率因數(power-factor, PF)。在類比電流迴路中,類比電流比較器為抑制雜訊的影響會加入磁滯比較區間 (hysteresis band),但是磁滯比較區間過大會導致系統輸入線電流失真;另外,由於交-直流轉換器中開關以及二極體的寄生效應使得在切換過程會產生高頻振盪,因此零電流偵測比較器的參考電壓大小會影響開關導通時刻,進而影響輸入電流的諧波失真,因此本論文針對磁滯比較區間以及參考電壓大小對於輸入電流諧波失真的影響進行分析,並選取適當的磁滯比較區間及參考電壓值以符合輸入電流規範。在數位電壓迴路中,類比數位轉換器(analog-to-digital converter, ADC)以及數位類比轉換器(digital-to-analog converter, DAC)量化效應會使電流命令波形失真,而進一步使輸入電流波形失真,因此本論文分析如何選取適當的取樣率(sampling rate)以及位元長度(bit length)。交-直流轉換器為了使輸入線電流不受市電兩倍頻漣波的影響,因而限制輸出電壓暫態響應速度,本論文加入帶拒濾波器於電壓迴路,濾除兩倍線頻,以提升系統的動態響應並且使線電流不受輸出電壓漣波的影響。由於在不同負載情況下,系統的動態特性也隨之變動,本論文提出負載適應增益調適機制,根據不同負載狀況,適時修正電壓控制器參數,使系統輸出動態響應於不同負載狀況下皆能維持穩定且快速的動態響應。本論文使用電路模擬軟體PSIM驗證所提出控制架構,在實驗驗證方面使用德州儀器 (Texas Instrument, TI)推出之數位信號處理器DSP(TMS320LF2407)實現數位電壓迴路,而類比電流迴路則以意法半導體(STMicroelectronis)推出的CRM PFC IC L6561實現。由模擬及實驗結果相互驗證本論文所提之控制架構;加入帶拒濾波器,當頻寬提昇至30 Hz時,輸入線電流的總諧波失真在滿載狀況下仍可維持在6 %;而負載適應增益調適機制,使得在輕載或重載情況下,進行相同負載變化量的切載測試,其動態響應速度以及穩定度皆相同,因此可顯示此控制架構的可行性及有效性。zh_TW
dc.description.abstractThis thesis develops a mixed-signal critical mode power-factor-correction (PFC) AC-DC converter with load adaptive gain scheduling. The peak current mode control is applied and analyzed by using the analog circuit. The voltage control loop is implemented in digital approach by using a digital notch filter and load adaptive gain adjustment to optimize the dynamic responses and maintain high power-factor (PF) with low total-harmonic-distortion (THD) in line current. This thesis analyzes the effect of the hysteresis band effect of the analog current comparator and the effect of the reference voltage in zero current detecting comparator on current command. In digital voltage loop, the proper quantization resolutions of both analog-to-digital converter (ADC) and digital-to-analog converter (DAC) are analyzed and determined. The digital voltage controller uses a digital notch filter to achieve fast dynamic response and still maintain low THD with high PF. An adaptive gain sheduling is applied for achieving the optimal dynamic response of the output voltage at different load variation conditions. The proposed mixed-signal PFC AC-DC converter with load adaptive gain scheduling has been verified by using computer simulation software (PSIM). This thesis uses the DSP EVM board TMS320LF2407 from Texas Instrument and the CRM PFC IC L6561 from STMicroelectronics to implement the experimental verification. The simulation and experimental results can verify the viability and effectiveness of the proposed control architecture.en_US
dc.language.isoen_USen_US
dc.subject邊界模式功率因數修正zh_TW
dc.subject混合信號控制zh_TW
dc.subject數位帶拒濾波器zh_TW
dc.subject負載適應增益調適zh_TW
dc.subjectcritical-conduction-mode PFCen_US
dc.subjectmixed-signal controlen_US
dc.subjectdigital notch filteren_US
dc.subjectload adaptive gain adjustmenten_US
dc.title具負載適應增益調適混合信號控制之邊界模式功率因數修正交-直流轉換器zh_TW
dc.titleDesign of a Load Adaptive Gain Adjustment Mixed-Signal Critical Mode PFC AC-DC Converteren_US
dc.typeThesisen_US
dc.contributor.department電控工程研究所zh_TW
Appears in Collections:Thesis


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