标题: | 具负载适应增益调适混合信号控制之边界模式功率因数修正交-直流转换器 Design of a Load Adaptive Gain Adjustment Mixed-Signal Critical Mode PFC AC-DC Converter |
作者: | 詹茗皓 Chan, Ming-Hao 邹应屿 Tzou, Ying-Yu 电控工程研究所 |
关键字: | 边界模式功率因数修正;混合信号控制;数位带拒滤波器;负载适应增益调适;critical-conduction-mode PFC;mixed-signal control;digital notch filter;load adaptive gain adjustment |
公开日期: | 2009 |
摘要: | 本论文研制具负载适应增益调适混合信号控制之边界模式功率因数修正(critical-mode power-factor-correction, CRM PFC)交-直流转换器,可应用于中低功率电子设备如:可携式电子产品或照明设备。本文所研制的混合信号控制其中电流回路使用类比方式实现,电压回路则以数位方式实现。本文并提出负载适应增益调适(load adaptive gain adjustment)以及带拒滤波器(notch filter)于数位电压回路,使系统输出电压可达到最佳动态特性且仍可使输入电流具备低总谐波失真(total-harmonic-distortion, THD)以及高功率因数(power-factor, PF)。在类比电流回路中,类比电流比较器为抑制杂讯的影响会加入磁滞比较区间 (hysteresis band),但是磁滞比较区间过大会导致系统输入线电流失真;另外,由于交-直流转换器中开关以及二极体的寄生效应使得在切换过程会产生高频振荡,因此零电流侦测比较器的参考电压大小会影响开关导通时刻,进而影响输入电流的谐波失真,因此本论文针对磁滞比较区间以及参考电压大小对于输入电流谐波失真的影响进行分析,并选取适当的磁滞比较区间及参考电压值以符合输入电流规范。在数位电压回路中,类比数位转换器(analog-to-digital converter, ADC)以及数位类比转换器(digital-to-analog converter, DAC)量化效应会使电流命令波形失真,而进一步使输入电流波形失真,因此本论文分析如何选取适当的取样率(sampling rate)以及位元长度(bit length)。交-直流转换器为了使输入线电流不受市电两倍频涟波的影响,因而限制输出电压暂态响应速度,本论文加入带拒滤波器于电压回路,滤除两倍线频,以提升系统的动态响应并且使线电流不受输出电压涟波的影响。由于在不同负载情况下,系统的动态特性也随之变动,本论文提出负载适应增益调适机制,根据不同负载状况,适时修正电压控制器参数,使系统输出动态响应于不同负载状况下皆能维持稳定且快速的动态响应。本论文使用电路模拟软体PSIM验证所提出控制架构,在实验验证方面使用德州仪器 (Texas Instrument, TI)推出之数位信号处理器DSP(TMS320LF2407)实现数位电压回路,而类比电流回路则以意法半导体(STMicroelectronis)推出的CRM PFC IC L6561实现。由模拟及实验结果相互验证本论文所提之控制架构;加入带拒滤波器,当频宽提升至30 Hz时,输入线电流的总谐波失真在满载状况下仍可维持在6 %;而负载适应增益调适机制,使得在轻载或重载情况下,进行相同负载变化量的切载测试,其动态响应速度以及稳定度皆相同,因此可显示此控制架构的可行性及有效性。 This thesis develops a mixed-signal critical mode power-factor-correction (PFC) AC-DC converter with load adaptive gain scheduling. The peak current mode control is applied and analyzed by using the analog circuit. The voltage control loop is implemented in digital approach by using a digital notch filter and load adaptive gain adjustment to optimize the dynamic responses and maintain high power-factor (PF) with low total-harmonic-distortion (THD) in line current. This thesis analyzes the effect of the hysteresis band effect of the analog current comparator and the effect of the reference voltage in zero current detecting comparator on current command. In digital voltage loop, the proper quantization resolutions of both analog-to-digital converter (ADC) and digital-to-analog converter (DAC) are analyzed and determined. The digital voltage controller uses a digital notch filter to achieve fast dynamic response and still maintain low THD with high PF. An adaptive gain sheduling is applied for achieving the optimal dynamic response of the output voltage at different load variation conditions. The proposed mixed-signal PFC AC-DC converter with load adaptive gain scheduling has been verified by using computer simulation software (PSIM). This thesis uses the DSP EVM board TMS320LF2407 from Texas Instrument and the CRM PFC IC L6561 from STMicroelectronics to implement the experimental verification. The simulation and experimental results can verify the viability and effectiveness of the proposed control architecture. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT079612515 http://hdl.handle.net/11536/41833 |
显示于类别: | Thesis |
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