一個應用在SATA-3.0且使用環型振盪器的6GHz全積體化展頻時脈產生器

Abstract

Serial Advanced Technology Attachment(SATA)已成為最重要的傳輸介面標準之ㄧ，其中傳輸量為6Gb/s的SATA-3.0更是下一代的主流規格。但晶片的時脈速度操作的越來越快，相對的高強度中心時脈信號所造成的電磁干擾(Electro-Magnetic Interference, EMI)現象也更加嚴重。相較於傳統的金屬屏蔽法(Metal Shielding)，展頻時脈產生器(Spread Spectrum Clock Generator, SSCG)是一種更有效降低晶片中EMI問題的方法。

本論文在TSMC-0.18um 1P6M CMOS製程下，設計出一個可運用在SATA-3.0介面的SSCG。其特色在於使用Ring-VCO直接產生6GHz時脈取樣，並且搭配三階的ΔΣ-modulator展頻調變電路來設計。同時也考量到最後晶片可能的主機板操作環境，針對此點作了Process Variation、Voltage、Temperature測試，也就是所謂的PVT分析，希望能提升對抗工作環境溫度變異的能力。這樣完成的SSCG，除了可避開傳統電感的精準製程特性要求外，更可以充分發揮Ring-VCO的各種優點:具有架構簡單容易實現，低面積使用，以及具備能夠在任意製程下作平移的條件。最後設計上將整體電路全積體化，對於將來的電路整合有極大的優勢。

在所有晶片量測中，每一顆晶片皆能夠符合SATA-3.0所訂立的各項規格要求，而各項常溫狀況下的平均量測結果如下，晶片面積為933um×933um，核心電路面積為500um×300um。晶片操作頻率為6GHz，工作電壓為1.8V，功率消耗為65.658mW(不包含輸出buffer)，EMI reduction在RBW=100K時為13.55dB，在RBW=10K時為24.30dB。PLL鎖定在6GHz的peak to peak jitter為16.256ps，rms jitter為2.152ps，展頻功能啟動時peak to peak jitter為21.541ps，而在展頻期間任意取250個週期的peak to peak jitter為10.106ps。在晶片溫度上升的測試中，只需將電壓調整為2.0V，PLL功能值到125°C都能夠正常工作產生6GHz時脈。

The serial advanced technology attachments (SATA) has become one of the most important interface standards, and SATA-3.0 with transmission rate 6 Gb/s is the major specifications in next generation. But when the chip operation clock speed works more rapid, the electro-magnetic interference (EMI) effect caused from high intensity peak energy of center frequency is more seriously too. Compare with conventional metal shielding, spread-spectrum clock generator (SSCG) is a more efficient method to reduce EMI effect in chip.

This thesis tries to design a SSCG can be used for SATA-3.0 in TSMC 0.18um 1P6M CMOS process which using a ring voltage controlled oscillators (Ring-VCO) at 6GHz operating frequency and chose the multi-stage-noise-shaping (MASH 1-1-1) delta-sigma modulator (3rd ΔΣ-modulator) for spread spectrum circuit. Because the design SSCG chip may operate on the motherboard, we also take the PVT analysis about process variation, voltage, temperature, and hope the design chip can compete working conditions about temperature change. The proposed SSCG avoid the inductors with precisely process characteristic so it has the Ring-VCO advantage of simple architecture, low area cost, and can be implemented in any CMOS process. We also make the chip fully integrated that has advantage of combine circuit in the future.

Finally, this thesis tests the entire design SSCG chip and all of the chip can match SATA-3.0 specifications in the room temperature. The average measurement results are list below. Chip area is 933um×933um and active area is 500um×300um. The chip operation frequency is 6GHz and consumes 65.658mW (no including output buffer) with 1.8V supply. EMI reduction is 13.55dB (RBW=100K) and 24.30dB (RBW=100K). The PLL locked on 6GHz clock peak-to-peak (pp) jitter is 16.256ps and rms jitter is 2.152ps. The pp jitter becomes 21.541ps when spread spectrum function work, and the random pp jitter with 250 cycles is 10.106ps. In the chip temperature rise test, the PLL function can still work at 6GHz clock until 125°C by change supply voltage to 2.0V.