並聯RC回授與變壓器雜訊抵消之超寬頻低雜訊放大器設計

Abstract

本論文提出了一個利用並聯RC回授與一個利用變壓器達成雜訊抵消的超寬頻低雜訊放大器設計。我們所提出的電路使用TSMC 0.18-μm CMOS 製程技術製作完成。 第一個電路我們使用RC並聯回授和一個源極電感來達成寬頻阻抗匹配並有效的降低雜訊。再利用並聯LC網路更進一步的壓制高頻雜訊達成很低的雜訊水平。量測結果為最低的雜訊指數為2.5 dB。在3.1-10.6 GHz的功率增益為10.9-13.9 dB。在3.1-15 GHz的輸入返回損耗為-9.4至-32.4 dB。在1.4V偏壓下的消耗功率為14.4 mW，整體面積為0.46 mm2。 第二個電路我們使用一個變壓器輸入級達成寬頻的雜訊抵消與輸入阻抗匹配，並只需要小的晶片面積與低的消耗功率。量測結果為最低的雜訊指數為3.8 dB。在3.1-10.6 GHz內的功率增益大於10.2 dB。在3.1-13 GHz內的輸入返回損耗低於-10.1 dB。在1.2V偏壓下的消耗功率為9.7 mW，整體面積為0.47 mm2。

In this thesis, a parallel-RC feedback and a transformer noise-canceling low noise amplifier for ultra-wide-band applications are presented. These propose circuits are implemented by the TSMC 0.18-μm CMOS process. In our first design, the parallel-RC shunt feedback with a source inductance is proposed to obtain the broadband input matching and to reduce noise level effectively. The parallel-LC network at drain is drawn to further suppress the high-frequency noise and a low noise level is achieved. Measured results show that minimum noise figure is 2.5 dB. The power gain is 10.9-13.9 dB from 3.1 to 10.6 GHz. The input return loss is below －9.4 dB from 3.1 to 15 GHz. It consumes 14.4 mW from 1.4 V supply voltage and occupies an area of only 0.46 mm2. In our second design, a transformer input stage is proposed to achieve broadband noise cancellation and input matching with small chip area and low power consumption. Measured results show that minimum noise figure is 3.8 dB. The power gain is more than 10.2 dB from 0.7 to 11.5 GHz. The input return loss is below －10.1 dB from 3.1 to 13 GHz. It consumes 9.7 mW from 1.2 V supply voltage and occupies an area of only 0.47 mm2.