氮化矽的氫與其應力對電晶體之影響

Abstract

首先，此研究確認了利用壓縮應力的氮化矽覆蓋層相較於伸張應力的氮化矽覆蓋層具有較高於N型金氧半場效電晶體耦合應力記憶技術的潛力。我們提出選用覆蓋層的方法應該被調整為使用應力改變量最大而非傳統挑選的初始應力最大的覆蓋層。並且，我們也發現到初始覆蓋層內的氫含量與隨後於退火時釋放的氫含量都會影響介面處懸浮鍵的鈍化。另一方面，退火後的應力而非應力改變量主導了閘極氧化層的劣化，進而導致劣化的閘極漏電流，在熱載子的加壓測試下顯現較高的臨限電壓位移，以及較差的閃爍雜訊。隨後，我們有系統的研究了不同反應氣體流量所沉積的氮化矽對複晶矽薄膜電晶體的鈍化效應。覆蓋了氮化矽的複晶矽薄膜電晶體能夠展現更佳的性能表現，壓抑電流突增效應(Kink effect)與改善閘極漏電流與閘極導致的汲極漏電流(DIBL)。由於不同的鈍化效應，覆蓋不同製程製備的氮化矽的原件會展現不同的效應。一物理機制被提出以解釋不完整的缺陷鈍化所導致的雙駝(double hump)現象。根據不同寬度的元件比較，不只是自由基在複晶矽內的缺陷鈍化作用會改善原件傳輸特性，閘極氧化層內的缺陷鈍化也會造成元件特性的改善。此外，覆蓋了氮化矽的原件，會提升對於正閘極電壓加壓測試，負閘極電壓加壓測試，與熱載子的加壓測試的免疫力。再者，此製程非常的簡單(不需要面臨電漿處理需要長時間問題)並且與傳統薄膜電晶體有很高的相容性。 隨後，此研究根據不同氮化矽厚度與不同的四乙氧基矽烷氧化層厚度討論了富含氫的氮化矽對於氫鈍化效率的議題，並得到了利用氮化矽是十分有效率的鈍化方法結論。氫會遭受隨後的退火製程導致的不穩定性也被詳細討論。結果顯示使用氮化矽覆蓋層可以避免氫從複晶矽通道中釋放。然而，移除氮化矽會使得氫在隨後的熱製程中釋放，而使得原件特性與對照樣本的特性相似。移除了氮化矽的樣本可以減緩對於熱載子的加壓測試的劣化。然而，氫釋放會劣化對於正偏壓溫度不穩定性加壓測試與負偏壓溫度不穩定性加壓測試的免疫力。兩種可能的機制被提出以解釋源自於氫釋放所導致的缺陷密度上升。此種不理想效應會影響熱載子的加壓測試，正偏壓溫度不穩定性加壓測試與負偏壓溫度不穩定性加壓測試。 最後，此研究討論了鄰近的薄膜對固相結晶與金屬側向結晶的影響。對於利用固相結晶的原件來說，將元件製備在氮化矽薄膜上會改變臨限電壓對溫度的相依性，其歸因於氫導致的成核點形成與氫或氮鈍化缺陷的行為。我們也發現在結晶前移除晶背後的非晶矽會影響原件的表現，其歸因於應力的影響。對於利用金屬側向結晶的原件來說，這些鄰近的薄膜不單會改變金屬側向結晶的速率，其也會改變電特性，故硬遮罩，緩衝氧化層，與絕緣墊片會因為不同的結晶特性而影響電特性。我們提出了三種可能的機制，包含了鎳捕捉，本質應力，與氫的參與，以釐清臨近薄膜的影響。

First, this dissertation certified that the compressive SiN capping layer has more potential than the tensile layer for fabrication using the stress memorization technique to enhance NMOS mobility. The mechanism that we have proposed implies that the conventional choice of the capping layer should be modulated from the point of view of the stress shift rather than using the highest tensile film. We also found that both the initial component of the deposited capping layer and the H released during annealing affected interface-state passivation. On the other hand, the annealed stress rather than the stress shift are responsible for degraded gate oxide quality, leading to the degraded gate leakage, higher threshold voltage shift under hot carrier stressing, and degraded flicker noise. Then, the effect of the flow rate of different reactant gases on the deposition of the SiN layer for passivation of poly-Si TFTs had systematically investigated. SiN passivation layers were found to yield better performance, suppress the kink effect, and improve the gate leakage current and gate induce drain leakage (GIDL) of polysilicon thin film transistors (poly-Si TFTs). The SiN passivation layers deposited under different deposition conditions possess different characteristics, due to their varying passivation effect. A physical mechanism is proposed to explain the double hump phenomenon induced by incomplete trap passivation. Based on the analysis of width dependence, the better performance of the samples with SiN passivation layers was attributed to not only the radical passivation of the defect states, but also the radical passivation of pre-existing defects in the gate oxide. Furthermore, using SiN passivation layers improves the immunity to positive gate bias stress, negative gate bias stress, and hot carrier stressing. Moreover, the manufacturing processes are simple (without the long processing time plasma treatment requires) and compatible with TFT processes. Then, this dissertation investigates the passivation efficiency of hydrogen by hydrogen-containing nitride, based on a comparison of different thicknesses of SiN or inserted TEOS oxide, indicating that hydrogen diffusion is efficient. Hydrogen instability induced by post annealing is also reviewed in detail. Results show that using a SiN capping layer can prevent the release of hydrogen from a poly-Si channel. However, removing this SiN capping layer allows the hydrogen release during post annealing, and the resulting device performance becomes comparable to the control sample. Samples with SiN capping layers removed can alleviate degradation by hot carrier stressing. However, hydrogen release reduces the immunity of PBTI and NBTI. Two possible mechanisms can explain the increased pre-existing defects associated with hydrogen release, which affects the hot carrier stressing, NBTI, and PBTI. Finally, this dissertation presented the impacts of the proximity layer on the SPC and MILC. For samples crystallized by SPC, the temperature dependence of threshold voltage are different for samples fabricated on the SiN proximity layer, and the formation of seed nuclei by hydrogen or traps passivated by hydrogen and nitrogen are responsible for this temperature dependence. Also, we found that removal of the backside a-Si before the crystallization would alter the performance originating from the stress viewpoint. For samples crystallized by MILC, The proximity layers not only affect the MILC growth rate, but also the electrical characteristics, meaning that the materials of the hard mask, the buffered layer, and the spacer affect the electrical characteristics due to the different crystallization conditions. Based on the comparison among the proximity layers, the SiN proximity layer is not suitable to be a hard mask or a spacer, due to the concern of crystallization condition. We proposed three reasonable mechanisms, including the gettering of Ni, the intrinsic stress, and the involvement of hydrogen, to make the deep understanding of the impacts of proximity layers.