具有超薄N2O退火氮化物閘極介電層與矽鍺通道之金氧半場效電晶體可靠度及通道厚度效應研究

Abstract

在本論文中，我們針對具有矽鍺(Si0.85Ge0.15)通道與超薄N2O退火氮化物閘極介電層(等效氧化層厚度約3.1奈米)之金氧半場效電晶體進行可靠度與通道厚度效應的研究。根據經驗公式，在矽基板與矽鍺通道接面處的價帶能階偏移量大約是0.1電子伏特，而閘極電流的傳導機制則主要是等效位能障約1.8電子伏特的FN穿遂機制。經過定電壓壓迫(CVS)及定電流壓迫(CCS)後，我們發現對N2O退火之矽化氮(SiN)閘極介電層並沒有造成明顯的損害，不過卻觀察到與電壓極性相關之電應力導致的漏電流(SILC)，此現象可藉由陽極電洞注入(AHI)模型加以解釋。隨後我們進行熱載子(hot-carrier)壓迫以及負電壓溫度產生不穩定性(NBTI)的電性量測，藉以評估矽鍺通道之p型金氧半場效電晶體的可靠度。在負電壓溫度產生不穩定性的壓迫下，我們已顯示電子缺陷(electron trapping)主導元件效能的破壞程度，而在熱載子壓迫的情況下則是由壓迫產生的界面狀態造成主要損害。由於電荷拉推電流(charge pumping current)的結果顯示Vg=Vd之壓迫產生最多的界面狀態，因此對於具有矽鍺通道及N2O退火矽化氮閘極介電層之p型金氧半場效電晶體的可靠度問題，我們認為Vg=Vd之壓迫情況導致元件效能最嚴重的損傷。另一方面，矽緩衝層的不完美晶格引起高密度錯排(dislocation)，並且降低驅動電流、轉導(transconductance)及等效載子遷移率，因此我們提出無矽緩衝層的矽鍺通道金氧半場效電晶體具有較佳的元件特性。此外，搭配5奈米和15奈米厚度的矽鍺通道金氧半場效電晶體，除了次臨界電壓振動(swing)低到67 mV/A，與30奈米矽鍺通道的元件相比，還具有較高的驅動電流、較低的界面狀態密度、較低的漏電密度、較高的轉導和較佳的等效載子遷移率。最後，對於未來次100奈米的技術領域，我們證明搭配矽鍺通道及N2O退火矽化氮閘極介電層之金氧半場效電晶體將具有高度的潛力。

We have investigated the reliability and the channel thickness effect of MOSFETs with Si0.85Ge0.15 channel and ultra-thin (EOT=3.1 nm) N2O-annealed SiN gate dielectric. The offset of valence band is about 0.1 eV. The FN tunneling dominates the conduction mechanism of the gate current with an effective barrier height of 1.8 eV. In addition, the results of CVS and CCS stressing show the insignificant degradation of the N2O-annealed SiN gate dielectric, and the polarity dependent SILC has been observed and explained by anode hole injection (AHI) model. The hot-carrier (HC) stressing and negative bias temperature instability (NBTI) are performed to evaluate the reliability of the SiGe channel pMOSFETs. We have demonstrated that electron trapping dominates the device degradation for the NBTI stressing and the interface state generation is dominant mechanism for the HC stressing. The results of the charge pumping current have shown the highest interface state density are generated after the device being stressed at Vg=Vd. Therefore, the stressing condition of Vg=Vd has been considered as the worst case for evaluating the reliability of the SiGe channel pMOSFET with N2O-annealed SiN gate dielectric. Because of the high dislocation density induced by the imperfect crystalline Si buffer layer, the driving current, transconductance, and effective mobility are degraded. Therefore, the SiGe channel MOSFETs without a Si buffer layer is proposed to have better device performance. Moreover, the MOSFETs with 5 and 15 nm SiGe channel have been shown smaller subthreshold swing of 67 mV/A, higher driving current, lower interface state density, lower leakage current, larger transconductance, and greater effective mobility as compared with the 30 nm SiGe channel devices. Finally, the MOSFETs with thin SiGe channel and N2O-annealed SiN gate dielectric have been demonstrated their potential for the sub-100 nm CMOSFET technology.