以圖型自同構為基礎之自動接線驗證樣本產生器

Abstract

在大型系統晶片 (system-on-a-chip, SoC) 設計中，嵌入式核心(embedded cores)的使用正大量的增加。高複雜度的系統晶片設計，使得設計驗證對系統整合者來說是個很大的挑戰。為了降低以嵌入式核心為基礎的設計驗證的複雜度，連接埠順序障礙模型 (port-order-fault，POF) 已經被提出，其對應的驗證向量產生器也已經發展好了。在本論文中，為了解決大型系統晶片連接驗證的問題，我們在連接埠順序障礙模型之下提出了一個以圖形自同構 (graph automorphism)為基礎的演算法來改善這個自動驗證向量產生器的效率。此外，這個演算法也可以運用於計算電路的輸入對稱的最大集合。我們測試了一些ISCAS-85和有較多輸入連接埠的MCNC電路。由實驗結果顯示，這個演算法可以在更少的時間下產生更有效的驗證向量。

Embedded cores are being increasingly used in the design of large system-on-a-chip (SoC). High complexities of SoC designs lead the design verification to be a challenge for system integrators. To reduce the verification complexity, the port-order-fault (POF) model has been proposed and the corresponding verification pattern generation has been developed for verifying core-based designs. This thesis proposes a graph automorphism-based algorithm to improve the efficiency of the automatic verification pattern generation (AVPG) for SoC interconnect verification based on the POF model. Furthermore, this algorithm can be applied to compute maximal sets of symmetric inputs of circuits. We conduct the experiments on ISCAS-85 and some MCNC benchmarks with large inputs of circuits. The experimental results demonstrate that our approach generates more efficient patterns with less CPU time.