互補式金氧半8位元40MHz取樣頻率管線化類比至數位轉換器之設計與分析

Abstract

本論文先對管線化類比至數位轉換器的架構加以描述，並同時將管線化類比至數位轉換器所可能造成誤差的原因加以探討，並提出解決方法。 本論文描述一個3.3V，8位元，40M sample/s管線化的類比至數位轉換器。本設計採用每級1.5位元的架構並運用數位錯誤修正的技術。主要的元件：餘數放大器（residue amplifier），比較器（comparator），正反器（D-flip-flop），加法器（adder）和時脈產生器（clock generator）。整個電路是由七級加上一個前端輸入保持電路所組成，全差動輸入範圍為-1V~+1V。餘數放大器的部分是以開關加電容配合放大器來實現。比較器的部分是以開關加電容配合動態比較器來實現。本架構多加入了一個不同相位的時脈,以減少比較器對餘數放大器的雜訊干擾,及確保比較器得到正確的值。 本架構使用台積電0.35um 2P4M互補式金氧半的製程，並以混合訊號全客戶式佈局實現。整個晶片佈局面積1.8mm x 1.8mm。以HSPICE作模擬,模擬的結果符合8位元解析度,40MHz取樣頻率,總功率消耗約為40mW。

In this thesis, the advantage and the architecture of the pipelined analog-to-digital converter (ADC) is described. Furthermore, the error source of the pipelined ADC is shown and discussed. And there are some solutions to these problems in this thesis.

We also illustrate a 3.3V, 8-bit, 40M sample/s CMOS pipelined ADC. The 1.5b/stage architecture with digital error correction is used in this ADC. The component in the ADC is the residue amplifier, the comparator, the D flip-flop, the adder and the clock generator. The ADC has 7 stages and a front-end sample-and-hold(S/H). The input is a fully differential format, the input range is -1V~+1V. The residue amplifier is implemented by the switch capacitor circuit. The comparator is implemented by the switch and capacitor and dynamic comparator. We add a new phase of clock to reduce the noise in residue amplifier from comparator.

The ADC was designed using TSMC 0.35um 2P4M CMOS process and mixed-signal full custom layout is applied. The chip area is 1.8mm x 1.8mm. The simulation is done by HSPICE. The specification of the ADC is 8bit resolution, 40M sampling rate, less than 40mW power consumption.