單晶片多處理器系統的通訊交換器設計

Abstract

隨著半導體製程的不斷進步，十年後，IC工程師將有可能在單一個晶片上整合上百個運算元件。此時，各個元件間的通訊將會成為影響系統效能的一大關鍵。IC設計工程師將需要一個能考慮通訊效能的系統設計方法。在這篇論文中，我們提出了一個適用於單晶片上多處理器的通訊架構。經由適當的設定，這個架構將可以提供不同的資料交換機制。由於我們的通訊架構具有能預測通訊效能的特性。系統設計者可以利用我們的架構在設計初期便分析系統效能以作出更好的決定。相關的實驗也顯示我們的架構能夠有效的傳遞資料。

Driven by the advance of semiconductor technology, it is possible to integrate hundreds of processing elements on a single chip in the next decade. At the moment, communication between the components will become the limiting factor for system performance and a communication-driven system design methodology will be needed. In this thesis, we propose an on-chip communication infrastructure for multi-processor system-on-chip. By appropriate configuration, the network can work as circuit switching, packet switching, and dedicated bus. System designers can also benefit from our framework to analyze the system performance and make better decisions at higher level because our platform exhibits predictable performance. The experiments of performance evaluation show that the communication fabrics can efficiently transfer data within system.