Solder Bump製程應用在Wafer Level CSP RDL結構可靠度提升 Study

Abstract

RDL (redistribution layer) 結構是傳統IC 金線封裝 wire bonding 轉換為覆晶封裝間之過渡性封裝產品。一般IC封裝之設計為將I/O pad佈局於IC 周圍，藉由打金線至導線架後，再進行封膠之傳統封裝方式。運用RDL 重新佈局技術 ( re-routing technology ) ，我們可將佈局於IC 周圍之pad 轉變為矩陣 ( area array )，而省去IC 為使用Flip chip 而需要於IC製造廠重新製作光罩，開發製程等費用. 與打金線之傳統封裝比較起來，應用Flip chip 科技不僅只具有封裝最小化高I/O，還具有較好之電性，散熱，與較好之信賴性等優點。研究中，將探討如何藉由材料的選用搭配，Bump 結構的設計以及製程的最佳化，以提升Solder bump RDL結構之信賴性。

在第一章導論中將說明WLCSP 的優點 , 傳統封裝設計下 , I/O pad 設計在邊緣 (peripheral IC pads ) , and RDL 技術重新佈局矩陣 ( area array ) .第2章中說明RDL 在製程中遇到的問題 , 包含adhesion 不良造成di-electric de-lamination , 提升adhesion , 以及不同bump structure 之比較 , 以及不同de-electric 的比較與選用 , 第三章說明實驗規劃 , 並以通過可靠度測試之完成樣品進行量測 , 來達到最終提升RDL 技術可靠度

本論文中之WLCSP 封裝產品將與FR4 機板結合，並不加上 underfill . 經本study後之最佳化產品已通過 wafer-level 以及 board-level 的可靠度測試，包含 1000 cycle，由 -55C 至 125C之temperature cycling。

RDL (Re-Distribution Layer) structure is an interim product to link up IC chip for wire bonding and flip chip assembly. We can perform area array solder bumps on a chip with peripheral IC pads by means of RDL rerouting technology, and the re-design and re-fabrication procedures of IC chip will not be required. The flip chip technology not only offers miniaturized packaging and higher I/O count but also has better electrical, thermal and reliability performances in comparison with traditional wire bonding. In this study, we investigate how to enhance the reliability property of solder bump with RDL structure by means of materials utilization, bump design and process optimization.

In Chapter 1, how WLCSP works and its benefits will be described. Under traditional gold wire design , the I/O pad of IC with peripheral pad turn to area array by RDL rerouting technology. In Chapter 2, the issues faces under RDL process re mentioned, including di-electric de-lamination due to bad adhesion, howthe adhesion improved, and the comparions between different bump structure, with various de-electric selection. Chapter 3 illustrates experiment design, Chapter 4 discusses the testing results from those samples which pass Reliability test , and result in raise Reliability of RDL technology .

The end product of this thesis is a WLCSP package composed of bare die onto FR4 substrate without underfill. The optimal design of RDL structure in the study has been qualified and passed wafer-level and board-level reliability tests, including temperature cycling test for 1000 cycles from -55C to 125C