具有加強轉換增益及雜訊相消機制的 V-band四倍頻器

Abstract

藉於操作在V-band 頻段以達到高資料傳輸已是近來的趨勢，本論文主要是設計一個低消耗功率的四倍頻器以做為在V-band 系統下的應用，如做為升頻混波器的本地震盪訊號等。此提出的四倍頻器為利用次諧波混合以增進其效能，包含詳盡的非線性分析與實驗結果，證明其能更有效率產生四倍頻信號。 在本論文中實現的晶片是使用TSMC 90-nm CMOS製程，輸入端的中心操作頻率為12.5 GH,在8 dBm 的基頻輸入功率下，輸出量得-20 dBm 的四倍頻訊號(包含3 dB的四相位產生器損耗以及9.5 dB的輸出級損耗)，功率消耗為2.8mW，在輸出雜訊抑制上，基頻與二倍頻以及三倍頻諧波的抑制比分別是53.5 dBc， 29.2 dBc及43 dBc，此外，在量測中也驗證我們提出的混頻架構可以在同樣的功率消耗下，比直接利用四階非線性特性產生四倍頻要高出4到7 dB的增益量。再者，整體直流功率消耗也控制在3mW以內，遠低於過去已提出的文獻。

For the reason that the recent trend of high data-rate transmission operating at V-band, this thesis aims at the design of a low-power frequency quadrupler on the application of V-band system such as a local oscillator signal for the up-conversion mixer. Moreover, the frequency quadrupler we proposed is by use of sub-harmonic mixing to improve the efficacy. Through the nonlinear analysis in detail and experiment result, we can demonstrate a truth that the generation efficiency is enhanced. The quadrupler circuit is designed and fabricated in TSMC 90nm CMOS technology. The input center frequency is 12.5 GHz. The measured output power level with an input signal of 8 dBm is -20 dBm( the date contains a loss of 3dB by differential-to-quadrature circuit and a loss of 9.5 dB due to the output buffer.), and the DC power consumption is 2.8mW. In respect of spurs rejection, the corresponding HRRs of f0. 2 f0, and 3 f0 are 53.5, 29.2, and 43 dBc, respectively. In addition, the measure date also verify our proposed architecture get 4 to 7 dB higher than the merely direct generation from the forth-order derivative, which is in a fair comparison III of equal power consumption with each other. Moreover, the DC power consumption is merely 3mW, which is lower than prior works.