單一晶界之多位元三維結構薄膜電晶體

Abstract

低溫複晶矽薄膜電晶體由於具有高載子遷移率的特性所以被廣泛的應用於主動式矩陣平面顯示器的開關元件。然而在朝向多功能系統整合型面板的發展趨勢下，除了高載子遷移率的運算單元外，同時也需要具有記憶功能的儲存單元。除了上述之特性外，在三維結構之堆疊上亦相當簡單，所以可微縮化的TFT-SONOS型記憶體，就很值得研究其在三維記憶體元件上之應用。而在二位元SONOS記憶體的運用中，需要透過通道熱電子注入(channel hot electron injection, CHEI)的寫入方式去製造出局部儲存電子的特性，但是隨著元件在通道長度的維縮下，第二位元效應(second bit effect)將會影響到SONOS進行二位元的一個操作，而且也會影響到4bits/cell的實現。 在本篇論文中，我們提出被稱為梯台式通道結晶法(Elevated Channel Method)的方式來控制準分子雷射結晶之晶粒成長方向與晶界位置，以避免一般準分子雷射結晶常出現的缺點，如隨機的晶界分佈、較窄的製程窗口等等。另外由於在晶界位置會形成一個突起(protrusion)，而這個突起具有加強電場的效果。也就是說我們具有著可以精準控制局部加強電場的一個技術，所以我們利用這項優點去搭配CHEI寫入技術，去創造一個更加不對稱的電荷儲存分佈，希望藉由這樣的電荷分佈去實現更好的二位元操作特性。而另外在TFT的運用部份我們也可以運用這種單一晶界在通道層中間的特性去實現一個具有更高載子遷移率的TFT特性。除此之外我們更進一步地希望結合3D IC的技術去將多位元TFT-SONOS進行單位面積下更高密度的堆疊。 第一部份我們比較了藉由梯台式通道結晶法去完成的幾種不同結構元件的TFT電性表現，我們可以發現在雷射能量為500 mJ/cm2，底閘極的場效載子移動率及次臨界擺幅分別是271 cm2/V-s及0.481 V/decade而上閘極的場效載子移動率及次臨界擺幅分別是320 cm2/V-s及0.438 V/decade，而雙閘極的結構由於有更好的閘極控制能力所以有一個更好的場效載子移動率 455 cm2/V-s 及次臨界擺幅0.386 V/decade。第二部份我們進行SONOS second bit effect 藉由逆向寫入與順向寫入的逆向讀取差值(two-bits margin)大小來判斷在SONOS部分二位元操作的表現。在這裡我們觀察底閘極，上閘極，雙閘極的two-bits margin分別是0.52 V, 0.22 V, 0.46 V，既然上閘極結構在通道中央有突起(protrusion)可加強寫入時的電場，因此我們選擇上閘極的結構，將上閘極做0.1 um及0.2 um的移動，在上閘極移動0.1 um及0.2 um的情況下，two-bits margin從原先的0.22 V分別增加到0.69 V及1.09 V，藉由這樣的結構大大的增加了二位元反向讀取時的差值，我們成功的透過一次的反向讀取就進行2位元的判讀。並且此種單一晶界控制搭配移動上閘極的結構(Single-Grain Boundary-Control with Offset-Top-Gate, SGBCOTG) 與底閘極的結構能夠在互不影響的情況下實現 4bits/cell 的目標。而在重複寫入/抹除耐久性的表現下，因為雙閘極多了一層nitride，所以會有較多deep traped的電子，所以在重複寫入的耐久性(endurance)的特性表現上較不理想。最後一部份我們則是透過層層堆疊(layer by layer stacking)的方式去將我們的TFT-SONOS去做堆疊探討其上下層的TFT或是SONOS的電性表現，藉由實驗結果我們可以得到對於上下層的元件而言，他們有很好的均勻性以及獨立性，所以我們一樣可以藉由層層堆疊之三維TFT-SONOS的結構在上下層元件互相不影響的情況下實現二維結構的2 bits單位元件面積下的4 bits操作。 綜合以上所述，3D結構的多位元TFT-SONOS記憶體由於有簡單的製程及更好的元件電特性，所以此技術之應用對於未來更高密度的記憶體需求而言勢必具有極大之應用潛力。

Low-temperature polycrystalling silicon (LTPS) thin film transistors (TFTs) have been widely used as the switching elements in active matrix displays due to their high field-effect mobility. In addition to high performance of operating elements as well as memory elements in the system on panel (SOP), TFT-SONOS memory is worthy to be investigated for the three dimensional applications owing to their features of being easily stacked. With the device dimension scaled down, the two-bits margin would be decreased due to the second bit effect increasing. Therefore, it was difficult to use the two bits mechanism (channel hot electron injection) with the symmetric SONOS structures; in the meantime, the 4 bits/cell target would hardly to achieve. In this thesis, we introduced the so-called elevated channel method to control the grain growth and the location of grain boundary, which could avoid many drawbacks of the conventional excimer laser crystallization, such as random grain boundaries, narrow process window, and etc. And there was a protrusion at the grain boundary with electric field enhanced effect. Consequently, we want to use the elevated channel method with excimer laser crystallization, and combine with an offset top gate mask design to fabricate asymmetric TFT-SONOS devices to increase the two-bits margin of SONOS memory. Furthermore, for the higher memory density demand in the future, we fabricated our device with 3D structures by using the layer by layer stacking technology to increase the memory capacity per unit area. In the first part, single grain boundary (SGB) bottom gate (BG), top gate (TG) and double gate (DG) TFT SONOS memory fabricated by excimer laser crystallization were investigated. As the excimer laser energy was 500 mJ/cm2 and the channel length was 1 um. The field-effect mobility and subthreshold swing of TFT-SONOS devices with bottom gate structure are 271 cm2/V-s and 0.481 V/decade, respectively. The field-effect mobility and subthreshold swing of TFT-SONOS devices with top gate structure are 320 cm2/V-s and 0.438 V/decade, respectively. In addition, to improve the gate controlling ability, we employ the double gate structure. The field-effect mobility and subthreshold swing of TFT-SONOS devices with Double gate structure are 455 cm2/V-s and 0.386 V/decade. In the second part, second bit effect was investigated by using both reverse read the SONOS with forward programming and reverse programming, respectively. The devices having single grain boundary with symmetric location under bottom gate, top gate and double gate structures fabricated by excimer laser crystallization studies with two-bits margin of 0.52 V, 0.22 V, and 0.46 V, respectively. Due to top gate has a protrusion in the channel middle, so the devices having single grain boundary with asymmetric location under offset top gate fabricated by excimer laser crystallization, the two-bits margin increased from 0.22 V to 0.69 V and 1.09 V with 0.1 um and 0.2 um top gate shift design, respectively. By using the large two-bits margin, the 2 bits (4 states) could be distiguished by once reverse read. And then to the endurance of SGB- bottom-gate, top-gate, double-gate, and offset-top-gate structures, the double gate structure has the worst endurance due to the more deep trapped electrons. In the last part, to achieve the high capacity demand the 3D structures with SGB-BG TFT-SONOS devices were implemented by layer by layer stacking technology. The two-bits margin of the top layer and the bottom layer devices were 0.61 V and 0.53 V, respectively. And the TFT-SONOS devices with 3D structure have good independence between top layer and bottom layer. Therefore, the 4 bits (16 states) were distinguished by twice read both top and bottom layer. To sum up, with the features such as simple process, high device performance, and large two-bits margin, the multi bits TFT-SONOS devices with 3D structures memory shows great potential in the 3D-IC applications.