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dc.contributor.author張雅婷en_US
dc.contributor.authorChang, Ya-Tingen_US
dc.contributor.author劉志尉en_US
dc.contributor.authorLiu, Chih-Weien_US
dc.date.accessioned2014-12-12T01:37:34Z-
dc.date.available2014-12-12T01:37:34Z-
dc.date.issued2011en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT079711630en_US
dc.identifier.urihttp://hdl.handle.net/11536/44330-
dc.description.abstract為了針對現今通用的NAL-NL1以及HSE處方有良好的補償匹配能力,在聽覺補償系統的設計上需要較高階數數的濾波器設計,但高階數的濾波器其延遲高且運算複雜度大。在使用分頻方式的聽覺補償系統中,為了減少濾波器組的運算量,使用的降運算量技巧會需要在延遲和運算量之間做取捨。因此我們考量在使用可控式濾波器的聽覺補償系統架構中,可以針對運算量的部分,用一個濾波器取代原來的濾波器組,藉此大幅降低運算量,並且不會額外增加聽覺補償系統的延遲時間。但此架構需要額外的運算量在係數內插的處理上,考量語音訊號不會有太大的變化量,不需要每筆取樣點都做內插計算,我們針對SPL的變化做偵測,並且大幅的降低係數內插的運算量。由於可控式濾波器是針對濾波器係數去做參數調配,因此我們可以針對不同的聽損情況,在1.5 dB的補償誤差限制下,找到最小的濾波器階數,同時也針對可控式濾波器的運算量以及延遲時間做最佳化。和分頻式的聽覺補償系統相比,針對不同的聽損情況,我們的設計可省下35% ~ 80%的運算量,延遲時間可由10 ms降到7.9 ~ 2.5 ms。並且在90奈米製程下進行實作,相較於先前的設計可省下27% ~ 30%的功率消耗。zh_TW
dc.description.abstractFor a good matching capability of the famous fitting formula NAL-NL1 and HSE, we need to design the auditory compensation with high-order filters. But the high-order filters also needs high delay and computational complexity. In the filter bank-based auditory compensation, it has a tradeoff between delay and computational complexity for the complexity reduction techniques. Considering the controllable filter architecture can reduce the computational complexity without compromise between delay and complexity. We use the architecture to reduce computational complexity from a set of filters to one filter. But it needs additional complexity to do coefficient interpolation for proper compensation at undefined input levels. Since the speech level would not change abruptly, we can interpolate coefficients just when the variation of input level is 3 dB and largely reduce the computational complexity of interpolation. Since the coefficients of the controllable filter are configurable. We can optimize the filter order for each hearing loss case. This optimization will also optimize the computational complexity and delay for each case. The proposed design can save 35% ~ 80% of computational complexity and reduce delay from 10 ms to 7.9 ~ 2.5 ms for different hearing loss cases. We implement the design in 90 nm CMOS technology. The design consumes only 190 ~ 198μW for 24 KHz audio signals. It saves about 27% ~ 30% power consumption compared to the filter bank-based auditory compensation with the filter bank [19].en_US
dc.language.isoen_USen_US
dc.subject數位助聽器zh_TW
dc.subject聽覺補償系統zh_TW
dc.subject低功耗zh_TW
dc.subject低運算複雜度zh_TW
dc.subjectdigital hearing aidsen_US
dc.subjectauditory compensationen_US
dc.subjectlow poweren_US
dc.subjectlow complexityen_US
dc.title適用於數位助聽器之低運算量可控式濾波器聽覺補償系統zh_TW
dc.titleComplexity-Effective Auditory Compensation with a Controllable Filter for Digital Hearing Aidsen_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
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