一個包含等化器及時脈與資料回復電路之高速序列傳輸接收機設計

Abstract

隨著資訊科技的進步，高速傳輸的需求與日俱增。但有限的通道頻寬將造成資料在傳送時遇到符際干擾(Inter-symbol interference, ISI)的現象，符際干擾可能造成資料判決上的錯誤。因此能補償通道損失的等化器在高速傳輸中扮演著重要的角色。 本論文提出了一個操作在8Gbps 的高速序列傳輸接收機。其中包含了類比等化器、決策回授等化器以及時脈與資料回復電路。類比等化器部份採用在回授路徑加入額外極點的方式以提供高頻增益峰化。決策回授等化器將運用sign-sign LMS演算法，因此將可適應性調整係數以解決通道頻寬不足所造成的後指標符際干擾問題。此外決策回授等化器將採用軟決策的架構以進一步使電路操作在更高的速度之上。接收端採用的時脈與資料回復電路能利用相位內插器來調整相位輸出，相位偵測器利用偵測資料斜率的機制可使相位鎖定在適當的地方。最後，我們也加入了展頻時脈追蹤的功能。 此電路採用UMC 55 nm 互補式金氧半導體製程技術實現，總面積為 1.0 X 1.85 mm2，在1.0V的操作電壓下，整體功率消耗為65.9mW。

With the advances in information technology, the demand of high speed transmission increase with each passing day. But the limitation bandwidth of the channel will causes the inter-symbol interference (ISI) when the data passes through the channel. ISI may cause wrong symbol detection. Therefore, the equalizer, which can be used to compensate for the channel loss, play an important role in high speed transmission. In this thesis, we propose a high speed serial link receiver that operates at 8 Gbps. The receiver includes an analog equalizer, a decision feedback equalizer(DFE) and a clock and data recovery circuit (CDR). The analog equalizer provides gain peaking at high frequency by putting an additional pole in the feedback path. The decision feedback equalizer will adjust the coefficient adaptively by sign-sign LMS algorithm to cancel the post-cursor ISI. Using soft-decision architecture will enhance the operation speed of the decision feedback equalizer. The clock and data recovery circuit can adjust the phase of the clock signal by using a phase interpolator. The phase detector of the CDR will let the clock phase lock at proper position by detecting the slope of the data. Finally, we also add an SSCG clock tracking function in the receiver. Implemented in a 55nm CMOS technology, the area is 1.0x1.85 mm2 including PAD, the chip consumes 65.9mW from 1V supply.