标题: | 三维积体电路的时序导向分割摆置演算法 Partition-Based Timing Driven Placement in Three-Dimensional Integrated Circuits |
作者: | 陈奕蓉 Chen, Yi-Rong 陈宏明 Chen, Hung-Ming 电子研究所 |
关键字: | 三维积体电路;区块放置;时序;3D IC;Placement;Timing |
公开日期: | 2010 |
摘要: | 在现今超大型积体电路设计中,由于制程技术进步和三维技术引进,藉由直通矽晶穿孔的堆叠结构发展,来达到三维空间的垂直整合。直通矽晶穿孔取代了二维空间中过长的绕线,如何有效适当的摆置区块和直通矽晶穿孔来改善时序问题。在此篇论文,我们将电路分层,逐一对每层执行切割摆置演算法的标准元件摆置,同时考量到摆置直通矽晶穿孔的对准条件限制,接着使用模拟退火法来减少绕线长度和优化时序,最后处理摆置的重叠问题。实验结果显示,三维积体电路较二维积体电路提升与改善整体效能。 The semiconductor technology has been advanced in modern VLSI design. Three-dimension (3D) concept imports an additional dimension for circuit design by using stack structures with through-silicon via (TSV). 3D ICs replace longer interconnect in 2D ICs with TSV cells. However, there are problems how to place cells and TSV cells to improve timing. In this thesis, we perform standard cell placement by min-cut partitioning for one layer after layer assignment and address alignment constraint at the same time. Then use simulated-annealing to optimize timing and reduces wirelength of interconnect. In the last, a legal placement by a greedy method removes operlap between cells and TSV cells. The experimental results show that 3D ICs improve wirelength and delay of critical path than 2D ICs. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT079711679 http://hdl.handle.net/11536/44375 |
显示于类别: | Thesis |
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