超低功率抗雜訊8T 靜態隨機存取記憶體的設計與實現

Abstract

低功率靜態隨機存取記憶體(SRAM)設計在手持式裝置高使用率的加持下已經漸漸成為主流，因為手提式製品都需要低功率晶片以延長工作時間。根據ITRS2005的預測，嵌入式靜態隨機存取記憶體佔整顆晶片面積將可達到90%，意思也就是說減少SRAM的功率損耗是降低晶片耗能最直接的辦法。 本篇論文提出一種降低單端讀取8T-SRAM陣列功率損耗的架構，藉由取得陣列keeper與記憶體單元漏電流的平衡，可以使記憶體陣列的virtual cell supply降低。 這樣將可以同時達到降低記憶體陣列的能量號損與改善記憶體單元的寫入能力。HSNM 由此論文建構的一套選擇keeper size檢測法，將被保證是安全無虞的。我們更提出了一個新的架構改善讀取動作的能量損耗。本篇論文的ULP-SRAM 與ALP-SRAM在跟對照組 Novel 8T比較下，皆可達到低功率的目的且最低操作電壓可達0.45V。

Low power design in Static Random Access Memory (SRAM) has become one of the mainstreams as a respond to the increasing usage of handheld device in that portable device requires a less power consumption chip to extend its working time. Nearly 90% area of a chip will be occupied by embedded SRAM in 10 years to come in accordance with ITRS2005 predictions which means that diminish power on SRAM will directly lead to chip power reduction. This thesis presents a power control technique to minimize the array power consumption of single-ended Read/Write 8T SRAM. By obtaining current balance between keepers of virtual cell supply and cell leakage, it allows a fall of virtual cell supply which is power supply of cell array. That leads to reduction of array power and improvement on write ability. Half Select Noise Margin (HSNM) is guaranteed safe by constructing an algorithm to size virtual cell supply keepers. To further improve read power, another structure is proposed to charge the virtual cell supply of selected column solely instead of all columns of selected rows. Both ALP and ULP SRAM achieves the power saving purpose compared to novel 8T SRAM and its VCCMIN is 0.45V.