數位校正式比較器及其在快閃型類比數位轉換器上的應用

Abstract

本論文發展一種數位式背景校正技術，用以削減比較器電路的輸入漂移電壓。這種校正技術不需中斷比較器的正常運作，因此特別適合運用在高速，低功率的場合。典型的應用例子是一個快閃型類比數位轉換器。首先，我們建構出一個隨機切換式比較器。由輸出碼的統計性密度，可以偵測該隨機切換比較器的漂移電壓極性。再依據漂移電壓的極性，設計一個校正迴路來逐步削減它，直到該比較器的輸入漂移電壓達到一個非常小的值為止。這個校正迴路的所有程序都利用數位電路進行，因此具有優越的可靠度與良率。

校正電路的效能優劣可以從漂移電壓的收斂速度，及其引發之跳動雜訊量的大小看出。對於前述的背景校正式比較器，這兩項效能指標由三個參數決定:輸入訊號的機率密度，漂移電壓的調整間距，以及應用在校正迴路中，一個雙向峰值偵測器的限制準位。

當應用在快閃型類比數位轉換器時，輸入訊號區域化的技巧可以大幅降低背景校正式比較器的跳動雜訊。這種技巧只要應用快閃型轉換器既有的溫度碼邊緣偵測器，配合校正迴路即可構成。因為溫度碼邊緣偵測器的介入，所可能引發之向上鎖定，進而迫使漂移電壓發散的效應，則可藉由安排相鄰比較器的隨機切換功能在統計上相互獨立來避免。

依據前述的校正技術，我們利用65奈米的金屬氧化物半導體製程，實作出一個每秒轉換20億次，具有6位元解析度的快閃型類比數位轉換器。轉換器所使用的比較器，採用無直流偏壓的類比閂鎖電路，以3 級串接的方式運作，並在第1級加入可微調漂移電壓的機制以配合校正迴路。在校正迴路的參數設定上，漂移電壓的調整間距為1/4LSB，雙向峰值偵測器的限制準位為16。

實作出之轉換器有效面積0.21x0.66平方釐米，供應電壓1.5V，消耗功率54mW。在校正迴路啟動前，DNL與INL分別是-1.0/+4.9LSB和-4.3/+5.4LSB 。校正迴路啟動後，DNL與INL分別降為-0.5/+0.6LSB和-0.4/+0.7LSB。對於一個32MHz的輸入訊號，背景校正技術使訊雜失真比從20.4dB 提昇到31.0dB。在每秒轉換20億次的速度下，有效解析度頻寬可超過Nyquist頻率。該轉換器的效能指標為每階次消耗0.93微微焦耳。

This thesis presents a digital background calibration technique to trim the input-referred offsets of a comparator circuit. The calibration does not interrupt the normal operation of the comparator, hence is suitable for high speed and power efficient applications such as flash analog-to-digital converters(ADC). For a random-chopping comparator, the polarity of its offset is detected by observing the code density of its comparison results. A calibration loop is then used to adjust the comparator offset so that the offset is minimized. All procedures in the calibration loop are performed in digital domain. This arrangement ensures excellent reliability and high yields. The calibration performance is characterized by the converging speed of the calibration loop and the fluctuation noise imposed to the input signal. These two performance indexes of a background-calibrated comparator (BCC) are determined by three parameters: the probabilistic distribution of input signal, the quantized step size of offset adjustment, and the threshold of an internal bilateral peak detector. In flash ADCs, the offset fluctuation of a BCC can be drastically reduced by input windowing mechanism, which is accomplished by incorporating the thermometer-code edge detector(TCED) into the calibration loop. When introducing the TCED, uncorrelated random chopping for neighboring BCCs is used to avoid upward locking phenomenon which may lock calibration. A 2Gsample/s 6-bit ADC with the developed calibration technique is fabricated using 65 nm CMOS technology. A circuit architecture with no DC bias and small transistor sizes is selected for comparators used in the ADC. The comparator includes modifications for variable offset mechanism and high common-mode rejection capability. The parameters for the calibration loop are 1/4 LSB for the quantized offset adjustment step, and 16 for the bilateral peak detector threshold. The active area of the fabricated ADC is 0.21×0.66mm2. Drawing from 1.5V supply voltage, the ADC consumes 54mW. Before activating the calibration, the DNL is -1.0/+4.9 LSB and the INL is -4.3/+5.4 LSB. After activating the offset calibration, the DNL becomes -0.5/+0.6 LSB and the INL is reduced to -0.4/+0.7 LSB. The calibration improves the SNDR from 20.4dB to 31.0dB with an input frequency of 32MHz. When operating at 2GS/s, the effective resolution of bandwidth extends over the Nyquist frequency. The figure-of-merit of the ADC is 0.93pJ/conversion-step.