功率積體電路之接面隔離研究

Abstract

功率積體電路乃是把高壓功率元件和CMOS低壓元件，整合在同一晶片上的積體電路，以提供使用者更完整的功能及更低廉的成本。但在整合時高壓功率元件與低壓電路或高壓功率元件之間的串音問題，使得元件隔離技術的發展成為功率積體電路設計上不可或缺的一環。本論文將針對此關鍵技術進行整合高壓功率元件與CMOS低壓電路之接面隔離技術研究。在接面隔離方面本論文藉由N型及P型保護環設計隔離結構。使用MEDICI電性模擬軟體模擬高壓功率元件在順向偏壓及反向偏壓下，不同的隔離佈局參數及偏壓對漏電流的影響。調變的佈局參數包括元件P-sink寬度、元件間距離、隔離結構(N型及P型保護環寬度)。論文中分析討論各項參數對隔離效果的影響，並於文末列舉最佳隔離方式的選擇，以做為將來設計功率積體電路時隔離結構設計的參考。

Since Power Integrated Circuit( PIC ) combines power devices with low voltage CMOS logic circuits on the same chip, it offers more intact function, and cheaper cost. However, the cross-talk happens between the power device and CMOS circuits or between one power device and the others. Therefore, the development of the isolation technology is indispensable in the power integrated circuit design. This thesis studies the junction isolation functions held between the power devices and CMOS logic circuits. The N-type and P-type guard ring are used to be the isolation structure. MEDICI, a 2-D device simulator, is used to simulate the relation of the leakage current between the layout parameters and the bias of the isolation structure when the power device is in forward bias and reverse bias, respectively. The design parameters of the layout include the width of P-sink, the distance between devices, and the changes of the widths of the N-type and P-type guard ring. We have simulated and analyzed variety of isolation performance resulted in the changes of the layout parameters and the bias of the isolation structure. Finally, we propose the most proper isolation design for each combination of high and low power devices.