可動態重複規劃之數位濾波處理器設計

Abstract

隨著數位訊號處理應用的日益廣泛，半導體製程技術的進步，在單晶片實現方式上的改進也顯得越來越重要。目前數位訊號處理器的實現方式，包括以特定應用積體電路的硬體實現，與以數位訊號處理器程式的軟體實現方式。前者實現上需要對演算法作分析，乃至於邏輯閘層面的電路設計；後者在使用上需要對處理器的架構及指令十分了解，並利用編譯器將工作排程之後下載至晶片上實現。針對以上兩者在設計時間上的冗長，過去的研究中，我們以派翠網路為模型，發展出一個可重複規劃的資料流處理器來實現數位訊號處理演算法。然而在先前的研究中，對於直接前傳路徑的實現，會發生硬體過於龐大，以及記憶體使用浪費的問題。本篇論文主要針對數位濾波器的實現，提出解決以上問題的方法，並配合硬體架構的改進，節省排程器以及記憶體使用的面積，以期使本架構更適合於處理數位濾波器的演算法。

The thesis proposes a dynamically scheduling methodology for DSP applications. With limited hardware resources available in digital filter design, it is necessary to schedule tasks on time with high efficiency. Traditionally, the scheduling is done by the compilation beforehand. Such a static scheduling approach is highly sensitive to the specification of digital filtering and the execution time of each task; thus, whenever the parameters of digital filtering is changed the compiling procedure needs to be walked through repeatedly. Designers usually spend much time on design and verification of DSP algorithm implementations. A reconfigurable dataflow architecture based on the Petri-Net model is presented and implemented in this thesis. Only the configuration data of the Petri-Net model needs to be updated during the transformation of different DSP algorithms, as long as the specification of throughput rate is matched. We have developed an area-efficient and memory-saving architecture with a novel folding approach on FIR filtering algorithm.