非同步封包交換晶片網路:協定與架構

Abstract

最近幾年晶片上面的核心數量日益增加，而設計的複雜度也隨著核心數的增加而提高。為了降低設計的複雜度以及提高矽智財(IP)的可重複使用性，設計者可以把數十個先前所設計的矽智財整合在SOC上。NOC則是支援這種整合方式的連結方式。 我們提出了使用了全雙軌協定的非同步晶片網路協定去定義在IP之間的一個完全非同步界面，提供了對使用者抽象的架構。我們同時也提出了資源網路介面 (RNI), 可以提供IP的重複使用以及隨插即用，適用於NoC架構的多核心處理器，另外RNI也提供了在所有的封包到達前，先將個別的封包暫存，避免單一封包的傳輸進而降低發出中斷的次數。

In recent years, the number of computing resources in a single chip has been enormously increased. The complexity of design is proportional to the number of cores. In order to reduce the design complexity and increase the re-usability of the IP blocks, designers can create systems-on-a-chip (SoC) by incorporating several dozens of IP blocks which are previously designed. Network-on-Chip (NoC) has been proposed to support the integration of multiple IP blocks in a single chip. We propose an asynchronous network-on-chips protocol (ANIP) which uses the four phase dual rail mechanism to provide an abstraction of the communication architecture. We also present a Resource Network Interface for a NoC based multiprocessor, which achieves the reuse of IP blocks, and buffers the receiving packets until all of the packets arrive to reduce the number of interruptions.