操作於次臨界電壓區之數位動態電壓調整系統

Abstract

本論文提出一個動態電壓調整系統(Dynamic Voltage Scaling)，我們藉由動態的調整數位電路上的工作電壓來克服當數位電路操作於次臨界電壓時，製程與溫度的變化對數位電路工作頻率造成的影響。我們讓數位電路允許的最高工作頻率能夠不因操作在次臨界電壓的條件下而產生劇烈的變化，使數位電路能夠工作在符合操作頻率要求的最低工作電壓以降低能量消耗。此系統是使用鎖頻迴路的概念來完成(Frequency Loop Lock)，利用頻率偵測器(Frequency Detector)來比較數位電路內的關鍵路徑(Critical Path)與外部參考頻率兩者之間的頻率高低後，適當的調整數位電路的操作電壓以改變關鍵路徑的延遲時間，使數位電路能夠工作在符合外部參考頻率要求的最低工作電壓，而不受製程與溫度變化的影響。動態電壓調整系統中的電壓調整電路，是使用交換式電容來當作電壓轉換器，使用交換式電容作為電壓轉換器的好處是，不需要使用到電感，並可將電容直接在IC內部製作完成，讓整個系統更容易達成系統晶片整合的目的。所提出的電路架構在TSMC 0.18μm 1P6M CMOS製程下模擬，經模擬結果顯示數位電路的操作電壓漣波可小於1mV，工作頻率誤差小於3%。

In this thesis we propose a dynamic voltage scaling system, we have by dynamically adjust the digital circuit operating voltage to overcome frequency impact when the digital circuit is operating in the sub-threshold region with process violation and temperature change. And maintain the operating frequency will not have a dramatic change due to operate in the sub-threshold region. This system use the concept of frequency loop lock, using the frequency detector to compare the critical path of the digital circuits and the reference frequency. Then appropriate adjustments to the operating voltage of the digital circuit to change the critical path delay, so that digital circuits can work at the reference frequency in minimum operating voltage and not restricted by the process and temperature variations. In dynamic voltage scaling system we use a switch capacitor voltage converter to adjust the operating voltage, the use of switched capacitor voltage converter as a benefit is not required to use the inductor. The capacitance can produced directly in the IC, SoC integration is easier to achieve the purpose. The proposed circuit architecture in TSMC 0.18μm 1P6M CMOS process simulated, the simulation results show that the operation of the digital circuit voltage ripple can less than 1mV, frequency error is less than 3%.