標題: 以Drive-in 製程的修正來改善 0.4μm P型金屬/氧化層/半導體(PMOS)臨界電壓電性的異常
Improved the Vth abnormality of 0.4μm P-type-Metal-Oxide- Semiconductor (PMOS) by modifing Drive-in process
作者: 林國芳
Lin, Kuo-Fang
吳耀銓
Wu, Yew-Chung
工學院半導體材料與製程設備學程
關鍵字: 以Drive-in 製程的修正來改善 0.4μm P型金屬/氧化層/半導體(PMOS)臨界電壓電性的異常;Improved the Vth abnormality of 0.4μm P-type-Metal-Oxide- Semiconductor (PMOS) by modifing Drive-in process
公開日期: 2010
摘要: 在本篇論文中,主要是0.4μm P型金屬/氧化層/半導體(PMOS) 臨界電壓,電性(threshold voltage of PMOS , Vtp) 異常,在電性超出規格(Out of Spec , OOS) 比例高達4.1%,且電性標準差過大造成 製程能力綜合指標(Potential within Capability , Cpk)=0.76變差(優良Cpk>1.33),這些產品電性 OOS 經由以報廢方式,在基於持續不斷改善的品質政策下,降低 OOS 比例及提昇 Cpk 能同時改善品質的 Quailty。 首先,在現況分析中,影響PMOS電性Vtp 相關製程站別利用統計變異數分析(Analysis of variance , ANOVA) 來做分析,在製程站別分析:4207站 Drive-in 製程機台權值比重佔了64%影響最大,其它製程機台權值比重分別小於15%影響不大,因此將針對4207站 Drive-in 製程機台進一步做分析。電性Vtp 再由 Drive-in 機台別及 run貨位置別做分析,在機台別分析:編號 甲和戊 標準差(Stdev)為0.05差異是最大,正常水準標準差(Stdev) ≦0.04。在run貨位置別分析:編號 甲和戊 最差位置C6與最好位置C4 mean 差異高達0.15V(電性絕對值C6比C4低),正常水準差異≦0.04。 我們利用二次離子質譜儀(secondary-ion mass spectrometry , SIMS) 分析機台編號 甲 和戊 最差位置C6 N-well ”phosphorous” 離子表面濃度偏低、電性Vtp 絕對值偏低現象以及學術理論,溫度對滲透深度(Penetration Depth) 所造成影響較大來推論主要為 Drive-in 製程爐管 熱預算(Thermal Budget) 過大。 此外,將利用實驗設計手法(Design of experiment , DOE) 做篩選實驗因子找出顯著因子(Drive-in)及最佳配方(溫度),且為了有效控制 Drive-in 製程的 Thermal Budget ,以量化數字表示實際模擬晶片受熱狀況,create 新的測試方法(1150℃, 1hour , 10L dry-oxidation)測量晶片厚度,可以有效模擬晶片受熱狀況。 最後,於產品做驗證機台編號 甲、乙、丙、丁和戊 爐管內run貨位置C1到C6改善後產品電性差距在1個標準差以內,PMOS電性整批性 OOS 比例降至0%,Cpk 提昇至1.58。同時提昇元件特性,例如:臨界電壓穩定、降低漏電流等。
In this thesis, fabrication and the Vth abnormality of 0.4μm P-type Metal-Oxide-Semiconductor (PMOS) has been studied. Initially, we discuss which factors affect volts for 0.4μm PMOS by device design and layout issue but we use analysis of variance to find more influence on Vth is Drive-in process. Position (C6) of machine No (甲 and 戊) are the most difference in analysis drive-in machine and position by (Analysis of Variance, ANOVA). It’s a simple method and low-cost to manufacture the PMOS then (secondary-ion mass spectrometry, SIMS) analysis surface concentration of N-well ”phosphorous”. The feature of process was the method of forming PMOS spacer of MOSFET. Simultaneously, we can simply guess that Thermal-Budget of drive-in is too high by appearance of low Vth and surface concentration low of SIMS analysis N-well”phosphorous”. Moreover, we find control factor (drive-in temperature) and the most prescription by design of experiment. Due to appearance of low Vth, surface concentration low of SIMS analysis and results design of experiment. Therefore, in order to solve this issue, we create the new test method(1150℃, 1hour, 10L dry-oxidation measure thickness of wafer) to control Thermal-Budget of Drive-in. Finally, we execute the the new test method treatment to further improve the production performance , such as stable of negative Vth , reduce leakage current and better subthreshold swing , etc.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079775501
http://hdl.handle.net/11536/46461
顯示於類別:畢業論文