CMOS 奈米元件閃爍雜訊與RTS之特性分析

Abstract

本論文針對不同世代之半導體製程技術 (0.25微米至40 奈米)，系統性地研究與分析閃爍雜訊特性。對於40奈米元件，當閘極面積變小時， 因缺陷 (trap) 僅存個位數, 若欲透過閃爍雜訊的量化而分析其行為與影響將遭受限制，為此，本論文將探討使用隨機電報訊號 (Random Telegraph Signal, RTS) 技術，進一步分析缺陷的特性與位置。於第二章中，針對相同世代製程下及不同世代製程之低頻雜訊密度與汲極電流、氧化層厚度的關係去探討。第三章中，我們使用40奈米製程氧化層厚度1.88奈米厚度之N型通道MOSFET及氧化層厚度 2.07奈米厚度之P型通道MOSFET的氧化層元件針對不同閘極偏壓之量測結果做研究分析，實驗最後推算出缺陷位於40奈米NMOSFET之氧化層中深度為6.6399埃(A)；位於40奈米PMOSFET之氧化層中深度為5.2355埃(A)。第四章為結論與未來研究的方向及展望。

In this thesis, systematic study and characterization of flicker noise for devices from 0.25um to 40nm technology nodes are conducted. For 40nm devices, when poly gate area becomes small, there is some limitation to characterize the device behaviors by quantifying the flicker noise due to the possible existence of single trap. For further investigation of 40nm devices, Random Telegraph Signal (RTS) is studied and used to estimate the trap behavior and location. Chapter 2 describes the relationship between noise spectral density, drain current and oxide thickness from the experiments in the same technology node or different technology nodes. In chapter 3, we use 40nm NMOSFET with oxide thickness 1.88nm and PMOSFET with oxide thickness 2.07nm measured by different bias for research. Finally, the estimate of the trap depth in the oxide layer of 40 nm NMOSFET is 6.63A; in 40 nm PMOSFET, it is 5.2355A. Chapter 4 is the conclusion and future work of this study.