用於腦電信號測量之高效能儀表放大器設計

Abstract

傳統的醫用腦電圖儀器巨大且昂貴;如何將硬體設計得平易近人，是系統設計上的重要考量之一。本論文針對腦電圖的使用,提出一個操作於 電源，低功率，低雜訊，高共模拒斥比的儀表放大器，可有效阻隔電極片的共模雜訊；由常規的三個運算放大器所組成。其中儀表放大器的最低共模拒斥有91.4 dB，input-referred noise（ 0.1 Hz到1 kHz）最高為12.7 ，總功率為0.7 mW。另外，運算放大器的開迴路增益是90.1 dB，單增益頻寬是9.8 MHz，共模拒斥比是92.6 dB，正電源供應抑制比是96.7 dB，input-referred noise（ 0.1 Hz到1 kHz）為7.9 ，總功率為0.23 mW。所提出的電路架構將被實現在TSMC CMOS 0.35 μm的製程。

Conventional clinical Electroencephalography device is huge and expensive. To fit those devices into our daily life is one of the important things in system design. A low-power, low-noise, high-common-mode-rejection-ratio instrumentation amplifier is presented, and can resists the common-mode disturbance efficiently. This instrumentation amplifier consists of three operational amplifiers and operates with a power supply from 1.65V to -1.65V. The instrumentation amplifier achieves 91.4 dB (lowest) common-mode rejection ratio, 12.7 input-referred noise (0.1 Hz to 1 kHz), and 0.7 mW total power dissipation. In addition, the operational amplifier achieves 90.1 dB open-loop gain, 9.8 MHz unity-gain bandwidth, 96.7 dB positive power-supply rejection ratio, 7.9 μV⁄(√(Hz ) )input-referred noises (0.1 Hz to 1 kHz), and 0.23 mW total power dissipation. This chip is to be realized in TSMC 2P4M 0.35 μm process.