22奈米高介電係數金屬閘極電晶體之正向偏壓溫度不穩定性分析及模擬

Abstract

在本篇論文中，我們提出了一個新的方法來模擬高介電係數CMOS在經過高溫偏壓操作後截止電壓的分佈。在量測上我們使用快速暫態的量測技術來減少量測的延遲時間，我們發現在經過高溫偏壓操作後由於電子被捕捉使得電流發生階梯狀衰減的現象。 為了了解在高溫偏壓操作時的單電子捕捉的現象，我們首先萃取由於電子被捕捉時電流的衰減量的機率分佈，接著我們也建立了在施壓(stress)及回復(recovery)時的時間模型。由以上實驗所得到的參數進行蒙地卡羅模擬來預測經過高溫偏壓操作後截止電壓的分佈。

In this dissertation a new method to predict the post-stress threshold voltage distribution is introduced. We proposed the fast transient measurement, which minimizes the switching delay between stress and measurement. Consequently, a staircase-like post-positive bias temperature (PBT) current instability caused by single electron trapping is investigated. To analyze the characteristic of PBTI stress induced threshold voltage degradation. First, we extract the probability distribution of the single electron trapping induced drain current degradation. Second, the time model is developed in stress and recovery phase. According to the characterization of the single charge phenomenon, we proposed a Monte Carlo simulation to simulate the post-stress threshold voltage distribution.