異質接面雙極性電晶體VBIC模型參數萃取與高速前置除頻器之實作

Abstract

本論文中，我們將探討和射頻積體電路設計有關的兩大主題。目前使用積體電路實作射頻電路最大的問題在於元件模型的不準確性，故第一個主題是利用新型的VBIC模型來模擬InGaP/GaAs異質接面雙極性電晶體特性，希望可以準確至幾個GHz。第二個部份則是高速前置除頻電路的設計、實作與量測的部份。 在前半段我們會討論在目前先進製程中的一些元件現象，尢其是Spice Gummel-Poon模型所沒有包含的部份。然後利用異質接面雙極性電晶體來測試VBIC模型是否可以準確的表現元件特性。由於VBIC在傳輸時間的部份繼承原本SGP模型的描述方式，所以在此部份是不足以完整描述元件現象。故我們再利用一個具物理意義的一維元件模型來模擬異質接面雙極性電晶體的傳輸時間特性。 在後半段，我們將設計並實作兩個能在射頻應用的高速前置除頻器。其一為利用SiGe製程的5GHz雙模數除頻器，它從5V的電源消秏31mA，以及在7.5GHz前低於20dB的輸入反射係數。第二個部份則是不同架構的除三電路特性比較，發現SHH架構可以有效的提昇電路最高工作頻率約30%。

In this paper, we will concentrate on two topics of Radio Frequency Integrated Circuits design issue. One is parameters extraction of InGaP/GaAs Heter-junction Bipolar Transistors using VBIC (Vertical-Bipolar Inter-Company) Model. The second is implementation and design of high speed prescaler. We will discuss about the effects which were implemented in the VBIC model but not include in Spice Gummel-Poon model. Then model InGaP/GaAs HBT using VBIC model to demo the capability of VBIC for both DC and AC characteristics. VBIC cannot model the HBT well in the part of transit time, since it use SGP equations which cannot tell the real case under different bias conditions to describe τf. Finally, a 1-D physical-based transit time model is used to model InGaP/GaAs HBT. The second part of this thesis is high speed prescaler. We will design and implement two prescaler for RF usage. The first is a 5GHz dual-modulus prescaler in SiGe technology consuming 31 mA from a 3.5 V supply. The prescaler (/4/5) can work up to 5GHz and the input return loss is below -7.5dB before 7.5GHz. The second one is comparison of two different topologies for truly 50% duty-cycle divide-by-3 circuit. The SHH topology can really extend input frequency range 30% for the divide-by-3.