建構低功率且穩健的時鐘樹

Abstract

在超大型積體數位電路中，時鐘樹的建立已然成為一門很大的學問。除了平 衡各個葉節點的延遲時間將其相位差降至最低，並要盡可能地降低功率消耗。當 元件的尺寸越來越小，製程變異對電路的效能影響也更加顯著。因此低功率消耗 且高度容忍製程變異的緩衝器時鐘數是不可或缺的。然而，目前缺少了有效的延 遲模組來提供準確的時序分析。先前的研究在合成時鐘樹的過程時，都必須要仰 賴電路模擬器使的相位差降到最低，卻花費了太多額外的執行時間。 為了提高執行時間以及達到低功率消耗的目標，在符合所有規定、時間相位差和電壓轉換速率限制的條件之下，我們提出了兩階段的方法來建構時鐘樹。首 先，利用艾蒙延遲模組(Elmore delay model)去建立有相同延遲時間的子樹。接 著用對稱的架構建立完上層的樹，並且使導線長度最小化。為了避免單一的時脈 源無法驅動過大的負載，我們在考量了電壓轉換速率限制、時間相位差、功率消 耗等因素情況後，在時鐘樹中插入緩衝器。 在這篇論文中，我們建構出一個低功率消耗的時鐘樹，不僅減少了額外去做 電路模擬程序的時間，並且時脈到達每一個元件的時間不會因為製程飄移而變異 太大。實驗結果與2010 年國際積體電路實體設計會議(ISPD)時鐘競賽的冠軍隊 伍相比，我們的方法平均可減少功率消耗58%。

Timing check is a critical stage in clock tree synthesis (CTS). Since no previous work has addressed on accurate timing model and most related works perform skew optimization by embedding SPICE simulation process into CTS flow, we should have more efficient timing check during CTS. To improve the run time and achieve the goal of minimizing power under all constraints, we propose a novel two-stage methodedology based on Elmore delay model and timing independent method. First, several sub-trees with similar delay under slew constraint are generated. Then we construct a top-level symmetrical tree that considers buffer sizing and wire-length minimization. Our approach not only significantly reduces the number of SPICE simulations, but also provides a high tolerance of variation and low power consumption. Experimental results are evaluated from the benchmarks of ISPD contest 2010. The proposed technique reduces 58% of power consumption on average and significantly improves the run time compared with the first place of the ISPD contest 2010.