應用於三維可程式邏輯閘陣列之熱感知擺放與繞線演算法

Abstract

新興的三維技術被認為是獲得更好的系統性能及更易於整合的解決方案，其堆疊多個晶粒(die)至單一晶片(chip)並利用直通矽穿孔(through-silicon vias, TSVs)做為垂直方向的連接。另一方面，可程式邏輯閘陣列(FPGAs)具有許多優點，是目前產品設計的主流選項之一。因此很自然的，三維可程式邏輯閘陣列(3D FPGAs)可以更進一步提升系統效能。然而，在三維整合技術裡，較高的功率密度(power density)與較長的散熱途徑(heat dissipation path)使得散熱問題較傳統的二維積體電路嚴重。因此發展具備熱感知(thermal-aware)的三維可程式邏輯閘陣列自動合成框架(framework)是相當重要的。針對這個目標，我們在這篇論文提出一系列適用於三維可程式邏輯閘陣列(3D FPGAs)的精準細微(fine-grained)熱電阻模型以及稱為TherWare的熱感知擺放(placement)與繞線(routing)演算法。在擺放時，我們不僅依照邏輯方塊(logic tile)之間的影響與每個方塊位置的散熱途徑來分配對應的邏輯區塊(Configurable Logic Block, CLB)，還會設法抑制因過長導線所增加的連線功率(interconnect power)；此外，在繞線階段更將同時考慮總消耗功率最簡化及功率分布之均勻度對於溫度的影響。由實驗結果可以證實，相較於現行已知的熱感知合成框架，經由TherWare所產生的合成結果在只需要增加些許電路延遲與程式執行時間的情況之下，最佳化過後的系統其最高溫、溫度標準差及最大溫度梯度都能夠被大幅地改善。

The emerging 3D technology, which stacks multiple dies within a single chip and utilizes through-silicon vias (TSVs) as vertical connections, is considered a promising solution for achieving better performance and easy integration. Meanwhile, field programmable gate array (FPGA) is one of the mainstream design solutions with lots of advantages. Therefore, 3D FPGA is a natural extension for further performance optimization. However, in 3D integration technology, the thermal issue is exacerbated mainly due to larger power density and longer heat dissipation path. As a result, the thermal-aware framework has been getting lots of attention in electronic designs. For this purpose, we propose a set of precise fine-grained thermal resistive models and a thermal-aware backend (placement and routing) flow named TherWare dedicated to 3D FPGAs in this thesis. In the placement stage, we not only consider the power distribution of logic tiles and heat dissipation path for each tile but also prevent the increase of interconnect power due to longer wirelength. In the routing stage, both power minimization and power distribution are considered. Finally, the experimental results show that our proposed TherWare can significantly improve maximum temperature, temperature deviation and maximum temperature gradient only with a minor increase in delay and runtime compared with the prior arts.